參數(shù)資料
型號: S1D13706
廠商: 愛普生(中國)有限公司
英文描述: S1D13706 Embedded Memory LCD Controller
中文描述: S1D13706 LCD控制器的嵌入式存儲器
文件頁數(shù): 48/152頁
文件大?。?/td> 1784K
代理商: S1D13706
Page 48
Epson Research and Development
Vancouver Design Center
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
1.
t8 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-11: Motorola REDCAP2 Interface Timing
Symbol
Parameter
2.0V
3.3V
Units
Min
Max
17
Min
Max
17
f
CKO
T
CKO
t1
t2
t3
t4
t5a
t5b
t5c
t5d
t6
t7
Bus Clock frequency
Bus Clock period
Bus Clock pulse width low
Bus Clock pulse width high
A[16:1], M/R#, R/W, CSn setup to CKO rising edge
A[16:1], M/R#, R/W, CSn hold from CKO rising edge
CSn asserted for MCLK = BCLK
CSn asserted for MCLK = BCLK
÷
2
CSn asserted for MCLK = BCLK
÷
3
CSn asserted for MCLK = BCLK
÷
4
EB0, EB1 asserted to CKO rising edge (write cycle)
EB0, EB1 de-asserted to CKO rising edge (write cycle)
D[15:0] input setup to 3rd CKO rising edge after EB0 or EB1
asserted low (write cycle) (see note 1)
D[15:0] input hold from 3rd CKO rising edge after EB0 or EB1
asserted low (write cycle)
OE, EB0, EB1 setup to CKO rising edge (read cycle)
OE, EB0, EB1 hold to CKO rising edge (read cycle)
D[15:0] output delay from OE, EB0, EB1 falling edge
(read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK (read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK
÷
2 (read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK
÷
3 (read cycle)
1st CKO rising edge after EB0 or EB1 asserted low to D[15:0]
valid for MCLK = BCLK
÷
4 (read cycle)
CKO rising edge to D[15:0] output in Hi-Z (read cycle)
MHz
ns
ns
ns
ns
ns
T
CKO
T
CKO
T
CKO
T
CKO
ns
ns
1/f
CKO
26
26
1
0
8
10
13
15
1
1
1/f
CKO
26
26
1
0
8
10
13
15
1
4
t8
1
0
ns
t9
23
8
ns
t10
t11
1
1
0
0
ns
ns
t12
4
29
3
10
ns
t13a
4.5CKO
+ 7
7CKO +
10
8.5CKO
+ 8
9CKO +
11
31
4.5CKO +
20
6.5CKO +
20
9.5CKO +
20
11.5CKO
+ 20
11
ns
t13b
ns
t13c
ns
t13d
ns
t14
4
1
ns
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