參數(shù)資料
型號: S1D13706
廠商: 愛普生(中國)有限公司
英文描述: S1D13706 Embedded Memory LCD Controller
中文描述: S1D13706 LCD控制器的嵌入式存儲器
文件頁數(shù): 38/152頁
文件大?。?/td> 1784K
代理商: S1D13706
Page 38
Epson Research and Development
Vancouver Design Center
S1D13706
X31B-A-001-09
Hardware Functional Specification
Issue Date: 2004/02/09
1.
t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
Table 6-6: Generic #2 Interface Timing
Symbol
Parameter
2.0V
3.3V
Unit
Min
Max
20
Min
Max
50
f
BUSCLK
Bus Clock frequency
T
BUSCLK
Bus Clock period
t1
Clock pulse width high
t2
Clock pulse width low
SA[16:0], M/R#, SBHE# setup to first BUSCLK rising edge
where CS# = 0 and either MEMR# = 0 or MEMW# = 0
SA[16:0], M/R#, SBHE# hold from either MEMR# or MEMW#
rising edge
t5
CS# setup to BUSCLK rising edge
t6
CS# hold from either MEMR# or MEMW# rising edge
t7a
MEMR#/MEMW# asserted for MCLK = BCLK
t7b
MEMR#/MEMW# asserted for MCLK = BCLK
÷
2
t7c
MEMR#/MEMW# asserted for MCLK = BCLK
÷
3
t7d
MEMR#/MEMW# asserted for MCLK = BCLK
÷
4
t8
MEMR# or MEMW# setup to BUSCLK rising edge
Falling edge of either MEMR# or MEMW# to IOCHRDY driven
low
Rising edge of either MEMR# or MEMW# to IOCHRDY high
impedance
SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and
MEMW# = 0 (write cycle) (see note 1)
t12
SD[15:0] hold from IOCHRDY rising edge (write cycle)
t13
MEMR# falling edge to SD[15:0] driven (read cycle)
t14
IOCHRDY rising edge to SD[15:0] valid (read cycle)
Rising edge of MEMR# to SD[15:0] high impedance (read
cycle)
MHz
ns
ns
ns
1/f
BUSCLK
22.5
22.5
1/f
BUSCLK
9
9
t3
1
1
ns
t4
0
0
ns
0
0
1
0
ns
ns
8.5
11.5
13.5
17.5
8
T
BUSCLK
T
BUSCLK
T
BUSCLK
T
BUSCLK
ns
11
13
17
2
1
t9
5
3
15
ns
t10
5
3
13
ns
t11
1
0
ns
1
4
0
3
ns
ns
ns
26
0
13
2
t15
5
33
3
12
ns
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