參數(shù)資料
型號(hào)： S1C6N3B0D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC54
封裝： DIE-54
文件頁(yè)數(shù)： 62/79頁(yè)
文件大?。?/td> 606K
代理商： S1C6N3B0D0A0100
S1C6N3B0 TECHNICAL MANUAL
EPSON
57
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Interrupt and HALT/SLEEP)
EIK00–EIK03: Interrupt mask registers (0E8H)
IK0: Interrupt factor flag (0EDH D0)
...See Section 4.3.4, "Control of input ports".
EIP0: Interrupt mask register (0E9H D2)
IP0: Interrupt factor flag (0EDH D1)
...See Section 4.5.6, "Control of I/O port".
EISIO: Interrupt mask register (0E9H D0)
ISIO: Interrupt factor flag (0ECH D0)
...See Section 4.9.5, "Control of serial interface".
EISW0, EISW1: Interrupt mask registers (0EAH D0 and D1)
ISW0, ISW1: Interrupt factor flags (0EEH D0 and D1)
...See Section 4.8.4, "Control of stopwatch timer".
EIT32, EIT8, EIT2: Interrupt mask registers (0EBH D0–D2)
IT32, IT8, IT2: Interrupt factor flags (0EFH D0–D2)
...See Section 4.7.3, "Control of clock timer".
4.11.5 Programming notes
(1) Restart from the HALT mode is performed by an interrupt. The return address after completion of the
interrupt processing will be the address following the HALT instruction.
(2) Restart from the SLEEP mode is performed by an input interrupt from the input port (K00–K03) or the
input-only port (P01 or P03 selected by mask option). The return address after completion of the
interrupt processing will be the address following the SLP instruction.
The SLEEP function can only be selected in the S1C6N3B0 CR oscillator model and the S1C6A3B0 by
mask option. It is not available in the S1C6N3B0 crystal oscillator model.
(3) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI
status. After completion of the interrupt processing, set to the EI status through the software as
needed.
Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning
of the interrupt processing routine.
(4) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask
register has been set to "1", the same interrupt will occur again if the EI status is set unless the inter-
rupt factor flag has been reset.
(5) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple
interrupt factor flags are to be assigned to the same address, perform the flag check after the contents
of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the
interrupt factor flag to be reset.
(6) Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will
not be generated. Be very careful when interrupt factor flags are in the same address.
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