參數(shù)資料
型號： S1C6N3B0D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC54
封裝： DIE-54
文件頁數(shù)： 60/79頁
文件大?。?/td> 606K
代理商： S1C6N3B0D0A0100
S1C6N3B0 TECHNICAL MANUAL
EPSON
55
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.11.1 Interrupt factors
Table 4.11.1.1 shows the factors that generate interrupt requests.
The interrupt factor flags are set to "1" depending on the corresponding interrupt factors.
The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to "1".
The corresponding mask register is "1" (enabled)
The interrupt flag is "1" (EI)
The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read.
At initial reset, the interrupt factor flags are reset to "0".
Note: Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1",
an interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request
will not be generated. Be very careful when interrupt factor flags are in the same address.
Table 4.11.1.1 Interrupt factors
Interrupt factor
Clock timer 2 Hz falling edge
Clock timer 8 Hz falling edge
Clock timer 32 Hz falling edge
Stopwatch timer 1 Hz falling edge
Stopwatch timer 10 Hz falling edge
I/O (P) port falling edge
Input (K) port falling edge
Serial I/F data transfer completion
Interrupt factor flag
IT2
(0EFH D2)
IT8
(0EFH D1)
IT32
(0EFH D0)
ISW1
(0EEH D1)
ISW0
(0EEH D0)
IP0
(0EDH D1)
IK0
(0EDH D0)
ISIO
(0ECH D0)
4.11.2 Specific masks for interrupt
The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt
mask registers are read/write registers. The interrupts are enabled when "1" is written to them, and
masked (interrupt disabled) when "0" is written to them.
At initial reset, the interrupt mask register is set to "0".
Table 4.11.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.
Table 4.11.2.1 Interrupt mask registers and interrupt factor flags
Interrupt mask register
EIT2
(0EBH D2)
EIT8
(0EBH D1)
EIT32
(0EBH D0)
EISW1
(0EAH D1)
EISW0
(0EAH D0)
EIP0
(0E9H D2)
EIK03*
(0E8H D3)
EIK02*
(0E8H D2)
EIK01*
(0E8H D1)
EIK00*
(0E8H D0)
ISIO
(0E9H D0)
Interrupt factor flag
IT2
(0EFH D2)
IT8
(0EFH D1)
IT32
(0EFH D0)
ISW1
(0EEH D1)
ISW0
(0EEH D0)
IP0
(0EDH D1)
IK0
(0EDH D0)
ISIO
(0ECH D0)
There is an interrupt mask register for each input port terminal.
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