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參數(shù)資料
| 型號： | S1C6N3B0D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC54 |
| 封裝： | DIE-54 |
| 文件頁數(shù)： | 55/79頁 |
| 文件大?。?/td> | 606K |
| 代理商： | S1C6N3B0D0A0100 |
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S1C6N3B0 TECHNICAL MANUAL
EPSON
51
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Serial Interface)
SCS1, SCS0: Synchronous clock selection (0E7H D1 and D0)
Selects the synchronous clock for the serial interface (SCLK).
Table 4.9.5.2 Synchronous clock selection
SCS1
1
0
SCS0
1
0
1
0
Mode
Master mode
–
Slave mode
Synchronous clock
CLK/2
CLK
–
External clock
Synchronous clock (SCLK) is selected from among the above 3 types: 2 types of internal clock and an
external clock.
At initial reset, external clock is selected.
SEN: Clock edge selection (0E7H D2)
Selects the timing for reading in the serial data input.
When "1" is written: Falling edge of SCLK
When "0" is written: Rising edge of SCLK
Reading: Valid
Selects whether the fetching for the serial input data to the registers (SD0–SD7) at the falling edge (at "1"
writing) or rising edge (at "0" writing) of the SCLK signal.
The input data fetching timing may be selected but output timing for output data is fixed at SCLK falling
edge.
At initial reset, rising edge of SCLK (SEN = "0") is selected.
SIOMODE: SIO terminal input/output control (0E9H D1)
Controls the I/O direction of the serial data line (P00).
When "1" is written: Output mode
When "0" is written: Input mode
Reading: Valid
The SIOMODE register is used to control the serial data direction when the P00 terminal is shared with
input and output as SIO. When "1" is written to the SIOMODE register, the serial interface is set to the
output mode and the SIO terminal becomes the serial data output terminal. When "0" is written, the serial
interface is set to the input mode and the SIO terminal becomes the serial data input terminal. The
content of the SIOMODE register is output to outside the IC via the MODE terminal (when the MODE
terminal has been set).
This control is not necessary when the SIN and SOUT terminals are provided separately.
At initial reset, input mode (SIOMODE = "0") is selected.
SCTRG, SCRUN: Clock trigger, Clock Run/Stop monitor (0E7H D3)
This is a trigger to start input/output of synchronous clock.
When "1" is written: Trigger
When "0" is written: No operation
Reading: Valid
When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK)
input/output is started.
As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed
prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writ-
ing/reading on data registers SD0–SD7.)
Supply trigger only once every time the serial interface is placed in the RUN state.
Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the
trigger.
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