參數(shù)資料
型號： S1C6N3B0D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC54
封裝： DIE-54
文件頁數(shù)： 40/79頁
文件大?。?/td> 606K
代理商： S1C6N3B0D0A0100
S1C6N3B0 TECHNICAL MANUAL
EPSON
37
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Clock Timer)
4.7 Clock Timer
4.7.1 Configuration of clock timer
The S1C6N3B0 Series has a built-in clock timer that uses the oscillation circuit as the clock source. The
clock timer is configured as a 7-bit binary counter that counts with a 256 Hz source clock from the
divider. The high-order 4 bits of the counter (16 Hz–2 Hz) can be read by the software.
Figure 4.7.1.1 is the block diagram of the clock timer.
128 Hz–32 Hz
Data bus
32 Hz, 8 Hz, 2 Hz
256 Hz
Clock timer reset signal
Oscillation
circuit
Interrupt request
Interrupt
control
16 Hz–2 Hz
Fig. 4.7.1.1 Block diagram of clock timer
Normally, this clock timer is used for all kinds of timing purpose, such as clocks.
Note: This manual describes frequencies and times when the crystal oscillation circuit (32.768 kHz) of
the S1C6N3B0 has been selected. Be aware that the frequencies and times vary when the
S1C6N3B0 CR oscillator model or the S1C6A3B0 is used.
See Section 4.2.6, "Frequency divider", for the input clock.
4.7.2 Interrupt function
The clock timer can generate interrupts at the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. The
software can mask any of these interrupt signals.
Figure 4.7.2.1 is the timing chart of the clock timer.
Clock timer timing chart
Frequency
Register
Address
0E4H
D0
16 Hz
D1
D2
D3
8 Hz
4 Hz
2 Hz
32 Hz interrupt request
8 Hz interrupt request
2 Hz interrupt request
Fig. 4.7.2.1 Timing chart of the clock timer
As shown in Figure 4.7.2.1, an interrupt is generated at the falling edge of the 32 Hz, 8 Hz, and 2 Hz
signals. At this point, the corresponding interrupt factor flag (IT32, IT8, IT2) is set to "1". The interrupts
can be masked individually with the interrupt mask register (EIT32, EIT8, EIT2). However, regardless of
the interrupt mask register setting, the interrupt factor flags will be set to "1" at the falling edge of their
corresponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to "1").
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