參數(shù)資料
型號： S1C6N3B0D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC54
封裝： DIE-54
文件頁數(shù)： 5/79頁
文件大小： 606K
代理商： S1C6N3B0D0A0100
S1C6N3B0 TECHNICAL MANUAL
EPSON
5
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER
2POWER SUPPLY AND INITIAL RESET
2.1 Power Supply
With a single external power supply (
) supplied to VDD through VSS, the S1C6N3B0 Series generates the
necessary internal voltages with the regulated voltage circuit (<VD1> for oscillator and internal circuit,
<VC1> for LCD) and the voltage booster circuit (<VC2, VC3> for LCD).
Figure 2.1.1 shows the power supply configuration.
Supply voltage: 6N3B0...0.8 to 3.6 V, 6A3B0...1.7 to 3.6 V
Note: External loads cannot be driven by the output voltage of the regulated voltage circuit and voltage
booster circuit.
See Chapter 6, "Electrical Characteristics", for voltage values.
External
power
supply
Internal
circuit
Oscillation
circuit
LCD system
voltage booster
Oscillation system
voltage regulator
LCD system
voltage regulator
VDD
V
OSC1, 2
COM0–3
SEG0–25(19)
D1
V
CA
CB
C1
C2
C3
LCD
driver
VSS
VC2, VC3
VC1
+
C3
C
4
5
C1
C2
Fig. 2.1.1 Configuration of power supply (when internal voltage regulator is selected as LCD power by mask option)
System reset
input
VDD
VD1
VC1, VC2, VC3
CA terminal
(for boosting)
Booster ON
Start VC2, VC3
output
HVLD ON
(by hardware)
Internal SR cancellation
(by hardware)
Power-on
VC1
"SR" ON
Min. 5 msec
VC2
XSR
VC3
VSS
VC2
VD1 (1.05 V)
VDD (0.8 V)
VC1
Vsta
≤ 3 sec
(OSC1: Crystal oscillation)
Vsta
≤ 3 msec (OSC1: CR oscillation)
Fig. 2.1.2 Sequence after power on (S1C6N3B0, VDD = 0.8 V)
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