參數(shù)資料
型號： S1C6N3B0D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC54
封裝： DIE-54
文件頁數(shù)： 53/79頁
文件大小： 606K
代理商： S1C6N3B0D0A0100
S1C6N3B0 TECHNICAL MANUAL
EPSON
49
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Serial Interface)
(3) Serial data input/output permutation
S1C6N3B0 Series allows the input/output permutation of serial data to be selected by mask option as
to either LSB first or MSB first. The block diagram showing input/output permutation in case of LSB
first and MSB first is provided in Figure 4.9.4.1.
SIN/SIO
Address [0E6H]
Address [0E5H]
Address [0E6H]
Address [0E5H]
Output
latch
Output
latch
SOUT/SIO
SD3 SD2 SD1 SD0
SD4 SD5 SD6 SD7
SD7 SD6 SD5 SD4
SD0 SD1 SD2 SD3
(In case of LSB first)
(In case of MSB first)
Fig. 4.9.4.1 Serial data input/output permutation
(4) SRDY signal
When the serial interface is used in the slave mode (external clock mode), SRDY is used to indicate
whether the serial interface is available to transmit or receive data for the master side (external) serial
device. The SRDY signal is output from the SRDY terminal (when the SRDY terminal is selected by
mask option).
The SRDY signal goes to "0" (low) when the serial interface becomes available to transmit or receive
data; normally, it is at "1" (high).
The SRDY signal changes from "1" to "0" immediately after "1" is written to SCTRG and returns from
"0" to "1" when "0" is input to the SCLK terminal (i.e., when the serial input/output begins transmit-
ting or receiving data). Moreover, when data is read from or written to SD4–SD7, the SRDY signal
returns to "1".
(5) Timing chart
The serial interface timing chart is shown in Figure 4.9.4.2.
SCTRG(W)
SCRUN(R)
SCLK
SIN/SIO
8-bit shift register
SOUT/SIO
ISIO
SRDY(slave mode)
a. SEN="1"
b. SEN="0"
SCTRG(W)
SCRUN(R)
SCLK
SIN/SIO
8-bit shift register
SOUT/SIO
ISIO
SRDY(slave mode)
Fig. 4.9.4.2 Serial interface timing chart
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