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參數(shù)資料
| 型號： | S1C6N3B0D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC54 |
| 封裝： | DIE-54 |
| 文件頁數(shù)： | 52/79頁 |
| 文件大小： | 606K |
| 代理商： | S1C6N3B0D0A0100 |
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48
EPSON
S1C6N3B0 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Serial Interface)
4.9.4 Data input/output and interrupt function
The serial interface of the S1C6N3B0 Series can input/output data via the internal 8-bit shift register. The
shift register operates by synchronizing with either the synchronous clock output from SCLK terminal
(master mode), or the synchronous clock input to SCLK terminal (slave mode).
The serial interface generates interrupt on completion of the 8-bit serial daata input/output. Detection of
serial data input/output is done by the counting of the synchronous clock (SCLK); the clock completes
input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates
interrupt.
The serial data input/output procedure data is explained below:
(1) Serial data output procedure
The S1C6N3B0 Series serial interface is capable of outputting parallel data as serial data, in units of 8
bits.
By setting the parallel data to data registers SD0–SD3 (0E5H) and SD4–SD7 (0E6H) individually and
writing "1" to SCTRG (0E7H D3), it synchronizes with the synchronous clock and serial data is output
at the SOUT/SIO terminal.
When the P00 terminal is used as SIO, it is necessary to set the serial interface to the output mode by
writing "1" to the SIOMODE register (0E9H D1) before transmitting. In the output mode, the MODE
terminal goes high level (when the MODE terminal has been set). This control is not necessary when
the P01 terminal is used as SOUT.
The synchronous clock used here is as follows: in the master mode, internal clock which is output to
the SCLK terminal while in the slave mode, external clock which is input from the SCLK terminal.
The serial data output from the SOUT/SIO terminal changes at the rising edge of the synchronous
clock.
When the output of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to
"1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register
EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor
flag is set to "1" after output of the 8-bit data.
(2) Serial data input procedure
The S1C6N3B0 Series serial interface is capable of inputting serial data as parallel data, in units of 8
bits.
By writing "1" to SCTRG, the serial data is input from the SIN/SIO terminal, synchronizes with the
synchronous clock, and is sequentially read in the 8-bit shift register.
When the P00 terminal is used as SIO, it is necessary to set the serial interface to the input mode by
writing "0" to the SIOMODE register before receiving. In the output mode, the MODE terminal goes
low level (when the MODE terminal has been set). This control is not necessary when the P01 terminal
is used as SOUT.
As in the above item (1), the synchronous clock used here is as follows: in the master mode, internal
clock which is output to the SCLK terminal while in the slave mode, external clock which is input
from the SCLK terminal.
The serial data is read to the built-in shift register at the falling edge of the synchronous clock when
SEN bit is "1" and is read at the rising edge of the synchronous clock when SEN bit is "0". Moreover,
the shift register is sequentially shifted as the data is fetched.
When the input of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to
"1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register
EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor
flag is set to "1" after input of the 8 bits data.
The data in the shift register can be read from data registers SD0–SD7 by software.
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