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參數(shù)資料
| 型號(hào)： | S1C6N3B0D0A0100 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC54 |
| 封裝： | DIE-54 |
| 文件頁(yè)數(shù)： | 54/79頁(yè) |
| 文件大小： | 606K |
| 代理商： | S1C6N3B0D0A0100 |
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50
EPSON
S1C6N3B0 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Serial Interface)
4.9.5 Control of serial interface
Table 4.9.5.1 shows the serial interface control bits and their addresses.
Table 4.9.5.1 I/O memory (Serial interface)
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
0E5H
SD3
SD2
SD1
SD0
R/W
SD3
SD2
SD1
SD0
– 2
High
Low
Serial interface
data register (low-order 4 bits)
LSB
0E6H
SD7
SD6
SD5
SD4
R/W
SD7
SD6
SD5
SD4
– 2
High
Low
MSB
Serial interface
data register (high-order 4 bits)
0E7H
SCTRG
SCRUN
W
R
SEN
SCS1
SCS0
R/W
SCTRG
SCRUN
SEN
SCS1
SCS0
– 2
0
Trigger
Run
–
Stop
Serial interface trigger (writing)
Serial interface status (reading)
Serial interface clock edge selection
Serial interface clock mode selection
0: Slave, 2: Master (CLK), 3: Master (CLK/2)
0E9H
0
EIP0
SIOMODE EISIO
RR/W
0 3
EIP0
SIOMODE
EISIO
– 2
0
–
Enable
Output
Enable
–
Mask
Input
Mask
Unused
Interrupt mask register (P0)
SIO terminal input/output control
Interrupt mask register (serial interface)
0ECH
0
ISIO
R
0 3
ISIO 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (serial interface)
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
SD0–SD3, SD4–SD7: Serial interface data registers (0E5H, 0E6H)
These are the data registers of the serial interface.
Writing
When "1" is written: High level
When "0" is written: Low level
Write serial data will be output to SOUT/SIO terminal. From the SOUT/SIO terminal, the data converted
into serial data as high (VDD) level bit for bits set at "1" and as low (VSS) level bit for bits set at "0".
Perform data writing only while the serial interface is standby status (i.e., the synchronous clock is
neither being input or output).
At initial reset, these registers will be undefined.
Reading
When "1" is read: High level
When "0" is read: Low level
The serial data input from the SOUT/SIO terminal can be read by this register.
The data converted into parallel data, as high (VDD) level bit "1" and as low (VSS) level bit "0" input from
SOUT/SIO terminal. Perform data reading only while the serial interface is standby status (i.e., the
synchronous clock is neither being input or output).
At initial reset, these registers will be undefined.
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