參數(shù)資料
型號： S1C6N3B0D0A0100
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC54
封裝： DIE-54
文件頁數(shù)： 61/79頁
文件大?。?/td> 606K
代理商： S1C6N3B0D0A0100
56
EPSON
S1C6N3B0 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.11.3 Interrupt vectors
When an interrupt request is input to the CPU, the CPU starts interrupt processing. After the program
being executed is suspended, interrupt processing is executed in the following order:
The address data (value of the program counter) of the program step to be executed next is saved on
the stack (RAM).
The interrupt request causes the value of the interrupt vector (page 1, 01H–08H) to be loaded into the
program counter.
The program at the specified address is executed (execution of interrupt processing routine).
Note: The processing in steps 1 and 2, above, takes 12 cycles of the CPU system clock.
Table 4.11.3.1 Interrupt vector addresses
Page
1
Step
00H
01H
02H
03H
04H
05H
06H
07H
08H
Interrupt vector
Initial reset
Clock timer interrupt
Stopwatch timer interrupt
Clock timer + Stopwatch timer interrupt
Input (K00–K03, P0n) interrupt
Input + Clock timer interrupt
Input + Stopwatch timer interrupt
Input + Clock timer + Stopwatch timer interrupt
Serial interface interrupt
4.11.4 Control of interrupt
Tables 4.11.4.1 show the interrupt control bits and their addresses.
Table 4.11.4.1 I/O memory (Interrupt)
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
0E8H
EIK03
EIK02
EIK01
EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
Enable
Mask
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
0E9H
0
EIP0
SIOMODE EISIO
RR/W
0 3
EIP0
SIOMODE
EISIO
– 2
0
–
Enable
Output
Enable
–
Mask
Input
Mask
Unused
Interrupt mask register (P0)
SIO terminal input/output control
Interrupt mask register (serial interface)
0EAH
0
EISW1
EISW0
RR/W
0 3
EISW1
EISW0
– 2
0
–
Enable
–
Mask
Unused
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
0EBH
0
EIT2
EIT8
EIT32
RR/W
0 3
EIT2
EIT8
EIT32
– 2
0
–
Enable
–
Mask
Unused
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
0EDH
00
IP0
IK0
R
0 3
IP0 4
IK0 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (P0)
Interrupt factor flag (K00–K03)
0ECH
0
ISIO
R
0 3
ISIO 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (serial interface)
0EEH
0
ISW1
ISW0
R
0 3
ISW1 4
ISW0 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
0EFH
0
IT2
IT8
IT32
R
0 3
IT2 4
IT8 4
IT32 4
– 2
0
–
Yes
–
No
Unused
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
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