
S1C6N3B0 TECHNICAL MANUAL
EPSON
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CHAPTER 4: PERIPHERAL CIARCUITS AND OPERATION (Stopwatch Timer)
ISW0, ISW1: Interrupt factor flags (0EEH D0 and D1)
These flags indicate the status of the stopwatch timer interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags (ISW0, ISW1) correspond to the 10 Hz and 1 Hz interrupts, respectively. With
these flags, the software can determine whether a stopwatch timer interrupt has occurred. However,
regardless of the interrupt mask register setting, these flags are set to "1" by the timer overflow.
They are reset by reading with the software.
Reading of interrupt factor flags are available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not
be generated. Be very careful when interrupt factor flags are in the same address.
At initial reset, these flags are set to "0".
SWRST: Stopwatch timer reset (0F9H D0)
This bit resets the stopwatch timer.
When "1" is written: Stopwatch timer reset
When "0" is written: No operation
Reading: Always "0"
The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset while
running, operation restarts immediately. Also, while stopped, the reset data is maintained.
This bit is write-only, and is always "0" when read.
SWRUN: Stopwatch timer run/stop (0F9H D1)
This bit controls run/stop of the stopwatch timer.
When "1" is written: Run
When "0" is written: Stop
Reading: Valid
The stopwatch timer runs when "1" is written to SWRUN, and stops when "0" is written.
When stopped, the timer data is maintained until the timer next Run or is reset. Also, when the timer
runs after being stopped, the data that was maintained can be used to resume the count.
If the timer data is read while running, a correct read may be impossible because of the carry from the
low-order bit (SWL) to the high-order bit (SWH). This occurs if reading has extended over the SWL and
SWH bits when the carry occurs. To prevent this, read after stopping, and then continue running. Also,
the stopped duration must be within 976 sec (256 Hz, 1/4 cycle).
At initial reset, this register is set to "0".