
S1C621C0 TECHNICAL MANUAL
EPSON
69
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.12.3 Interrupt vector
When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program
being executed is terminated, the interrupt processing is executed in the following order.
The address data (value of program counter) of the program to be executed next is saved in the stack
area (RAM).
The interrupt request causes the value of the interrupt vector (page 1, 02H–0BH) to be set in the pro-
gram counter.
The program at the specified address is executed (execution of interrupt processing routine by soft-
ware).
Table 4.12.3.1 shows the correspondence of interrupt requests and interrupt vectors.
Note: The processing in and above take 12 cycles of the CPU system clock.
Table 4.12.3.1 Interrupt request and interrupt vectors
Interrupt request
Remote controller
R/F converter
K10–K13 input
K00–K03 input
Clock timer
Priority
High
↑
↓
Low
Interrupt vector
102H
104H
106H
108H
10AH
The four low-order bits of the program counter are indirectly addressed through the interrupt request.
4.12.4 Control of interrupt
Tables 4.12.4.1(a) and (b) show the interrupt control bits and their addresses.
Table 4.12.4.1(a) Control bits of interrupt (1)
D3
D2
D1
D0
Name
Init
1
0
*1
90H
SIK00
SIK03
SIK02
SIK01
SIK00
0
Enable
Disable
SIK01
SIK02
SIK03
92H
KCP00
R/W
KCP03
KCP02
KCP01
KCP00
KCP01
KCP02
KCP03
1
*7
R/W
Input comparison register (K00–K03)
94H
SIK10
SIK13
SIK12
SIK11
SIK10
0
Enable
Disable
SIK11
SIK12
SIK13
96H
KCP10
R/W
KCP13
KCP12
KCP11
KCP10
KCP11
KCP12
KCP13
1
R/W
Input comparison register (K10–K13)
Address
Comment
Register
Interrupt selection register (K00–K03)
Interrupt selection register (K10–K13)
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read