參數(shù)資料
型號： S1C621C0D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74
封裝： DIE-74
文件頁數(shù)： 78/108頁
文件大?。?/td> 992K
代理商： S1C621C0D
S1C621C0 TECHNICAL MANUAL
EPSON
63
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (R/F Converter)
IRF: Interrupt factor flag (F9HD0)
This flag indicates the status of the R/F converter interrupt.
When "1" is read:
Interrupt has occurred
When "0" is read:
Interrupt has not occurred
Writing:
Invalid
IRF is set to "1" when R/F conversion is terminated, when the time base counter overflows while counting
the oscillation of the reference resistance, or the measurement counter overflows while counting the
oscillation of the sensor.
From the status of this flag, the software can decide whether an R/F converter interrupt has occurred.
Further this flag is set in the above timing regardless of the interrupt mask register setting.
This flag is reset when the software has read it.
Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be
generated.
After an initial reset, this flag is set to "0".
4.10.6 Programming notes
(1) Depending on the initial value of the measurement counter (MC), the measurement counter (MC) or the
time base counter may overflow while the CR oscillation clock is being counted. When setting the initial
value, pay attention to CR oscillation frequency, its fluctuation range and the input clock frequency of
the time base counter. If an overflow occurs, R/F conversion is terminated immediately. When the R/F
conversion result (measurement counter value) is read, check the overflow flags (OVMC and OVTBC).
(2) When an interrupt occurs by the counter overflow, the same interrupt will occur if the overflow flag
(OVMC or OVTBC) is not reset. Be sure to check and reset to "0" (writing "1") the overflow flag when
the R/F converter interrupt occurs.
(3) When using the OSC3 clock as the time base counter input clock, the OSC3 oscillation circuit must be
ON (OSCC = "1") before starting R/F conversion.
It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes.
Consequently, when starting a remote output, secure 5 msec or more waiting time for oscillation
stabilization after turning the OSC3 oscillation ON.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics and
conditions of use, so allow ample margin when setting the waiting time.
(4) Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will
not be generated.
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