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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 39/108頁 |
| 文件大小： | 992K |
| 代理商： | S1C621C0D |
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28
EPSON
S1C621C0 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.6.4 Control of I/O ports
Table 4.6.4.1 lists the I/O ports' control bits and their addresses.
Table 4.6.4.1 Control bits of I/O ports
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
IOC00
PUL00
P00
IOC03
IOC02
IOC01
IOC00
PUL03
PUL02
PUL01
PUL00
P03
P02
P01
P00
0
1
Output
On
High
Input
Off
Low
IOC01
PUL01
P01
IOC02
PUL02
P02
IOC03
PUL03
P03
B0H
B1H
B2H
*7
I/O control register (P00–P03)
Pull up control register (P00–P03)
I/O port P00–P03
R/W
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
P00–P03: I/O port data (B2H)
I/O port data can be read and output data can be set through these ports.
When writing data
When "1" is written:
High level
When "0" is written:
Low level
When an I/O port is set to the output mode, the written data is output unchanged from the I/O port
terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written,
the level goes low (VSS).
Port data can be written also in the input mode.
When reading data out
When "1" is read:
High level
When "0" is read:
Low level
When the I/O port is in the input mode the voltage level being input to the port terminal can be read out;
in the output mode the register value can be read. When the terminal voltage in the input mode is high
(VDD) the port data that can be read is "1", and when the terminal voltage is low (VSS) the data is "0".
When PUL register is set to "1", the built-in pull up resister goes ON during input mode, so that the I/O
port terminal is pulled up. The gate floating has not occur by the input control signal even if the PUL
register is set to "0" and no pull up register is set.
When input terminals are changed from low to high by pull up resistor, the rise of the waveform is delayed
on account of the time constant of the pull up resistor and input gate capacitance. Hence, when fetching
data during input mode, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
Waiting time = RIN
× (CIN + load capacitance on board) × 1.6 [sec]
RIN: pull up resistance (Max. value)
CIN: terminal capacitance (Max. value)
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