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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 16/108頁 |
| 文件大小： | 992K |
| 代理商： | S1C621C0D |
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S1C621C0 TECHNICAL MANUAL
EPSON
7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a low level (VSS). After that the initial
reset is released by setting the reset terminal to a high level (VDD) and the CPU starts operation.
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when fOSC1 = 32 kHz) is needed until the internal initial reset is
released after the reset terminal goes to high level. Be sure to maintain a reset input of 0.1 msec or more.
However, when turning the power on, the reset
terminal should be set at a low level as in the
timing shown in Figure 2.2.1.1.
VDD
RESET
2.0 msec or more
2.2 V
0.4VDD
0.1VDD or less (low level)
Power on
Fig. 2.2.1.1 Initial reset at power on
The reset terminal should be set to 0.1VDD or less
(low level) until the supply voltage becomes 2.2 V
or more.
After that, a level of 0.4VDD or less should be
maintained more than 2.0 msec.
2.2.2 Watchdog timer
If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial
reset signal. See Section 4.2, "Resetting Watchdog Timer", for details.
As with the oscillation detection circuit, you should not do an initial reset at power-on using this function.
2.2.3 Internal register at initial resetting
Initial reset initializes the CPU as shown in the table below.
Table 2.2.3.1 Initial values
*
See Section 4.1, "Memory Map".
2.3 Test Terminal (TEST)
This terminal is used at the time of the factory inspection of the IC. During normal operation, connect the
TEST to VDD.
Program counter step
Program counter page
New page pointer
Stack pointer
Index register IX
Index register IY
Register pointer
General-purpose register A
General-purpose register B
Interrupt flag
Decimal flag
Zero flag
Carry flag
CPU core
Name
Number of bits
8
4
8
11
4
1
Setting value
00H
1H
Undefined
0
Undefined
Symbol
PCS
PCP
NPP
SP
IX
IY
RP
A
B
I
D
Z
C
RAM
Display memory
Other peripheral circuits
Peripheral circuits
Name
Number of bits
4
—
Setting value
Undefined
*
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