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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 23/108頁 |
| 文件大?。?/td> | 992K |
| 代理商： | S1C621C0D |
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S1C621C0 TECHNICAL MANUAL
EPSON
13
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)
4.2 Resetting Watchdog Timer
4.2.1 Configuration of watchdog timer
The S1C621C0 incorporates a watchdog timer as the source oscillator for OSC1 (dividing clock = 1 Hz). The
watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3 or 4 seconds,
the initial reset signal is output automatically for the CPU.
Figure 4.2.1.1 is the block diagram of the watchdog timer.
1 Hz
Watchdog timer reset signal
Initial reset signal
Watchdog
timer
WDRST
fOSC1
OSC1
Oscillation circuit
Dividing
circuit
Fig. 4.2.1.1 Watchdog timer block diagram
The watchdog timer, configured of a 2-bit binary counter, generates the initial reset signal internally by
overflow of the last stage (1/4 Hz).
Watchdog timer reset processing in the program's main routine enables detection of program overrun, such
as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated
where periodic processing takes place, just as for the timer interrupt routine.
The watchdog timer operates in the HALT mode. If the HALT status continues for 3 or 4 seconds, the initial
reset signal restarts operation.
4.2.2 Control of watchdog timer
Table 4.2.2.1 lists the watchdog timer's control bit and its address.
Table 4.2.2.1 Control bit of watchdog timer
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
WDRST: Watchdog timer reset (C6HD0)
This is the bit for resetting the watchdog timer.
When "1" is written:
Watchdog timer is reset
When "0" is written:
No operation
Reading:
Always "0"
When "1" is written to WDRST, the watchdog timer is reset, and the operation restarts immediately after
this. When "0" is written to WDRST, no operation results.
This bit is dedicated for writing, and is always "0" for reading.
4.2.3 Programming note
When the watchdog timer is being used, the software must reset it within 3-second cycles.
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
WDRST
W
0
WDRST
–
Reset
–
0
R
0
C6H
*2
*5
*7
Unused
Watchdog timer reset
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