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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 17/108頁 |
| 文件大?。?/td> | 992K |
| 代理商： | S1C621C0D |
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8
EPSON
S1C621C0 TECHNICAL MANUAL
CHAPTER 3: CPU, ROM, RAM
CHAPTER
3 CPU, ROM, RAM
3.1 CPU
The S1C621C0 employs the 4-bit core CPU S1C6200A for the CPU, so that register configuration, instruc-
tions and so forth are virtually identical to those in other family processors using the S1C6200A.
Refer to "S1C6200/6200A Core CPU Manual" for details about the S1C6200A.
Note the following points with regard to the S1C621C0:
(1) The SLEEP operation is not assumed, so the SLP instruction cannot be used.
(2) RAM is set up to four pages, so only the three low-order bits are valid for the page portion (XP, YP) of
the index register that specifies addresses. (The one high-order bit is ignored.)
3.2 ROM
The built-in ROM, a mask ROM for loading the program, has a capacity of 4,096 steps, 12 bits each. The
program area is configured of 16 pages (0–15) with 256 steps each (00H–FFH). After initial reset, the
program beginning address is page 1, step 00H. The interrupt vector is allocated to each page 1, steps 02H–
0BH.
Fig. 3.2.1 ROM configuration
3.3 RAM
The RAM, a data memory storing a variety of data, has a capacity of 208 words, each of four bits. When
programming, keep the following points in mind.
(1) Part of the data memory can be used as stack area when subroutine calls and saving registers, so be
careful not to overlap the data area and stack area.
(2) Subroutine calls and interrupts take up three words of the stack area.
(3) The data memory 000H–00FH is for the register pointers (RP), and is the addressable memory register
area.
Program start address
Interrypt
vector
area
Page 0
Step 00H
Bank 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
Page 9
Page 10
Page 11
Page 12
Page 13
Page 14
Page 15
Step 01H
Step 0BH
Step 0CH
Step FFH
12 bits
Step 02H
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