參數(shù)資料
型號(hào)： S1C621C0D
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74
封裝： DIE-74
文件頁(yè)數(shù)： 15/108頁(yè)
文件大?。?/td> 992K
代理商： S1C621C0D
6
EPSON
S1C621C0 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.1.1 Voltage <VD1> for oscillation circuit and internal circuits
VD1 is the voltage for the oscillation circuit and the internal logic circuits, and is generated by the oscillation
system regulated voltage circuit for stabilizing the oscillation.
Making VSS the standard (GND level), the oscillation system regulated voltage circuit generates VD1 from
the supply voltage that is input from the VDD–VSS terminals.
2.1.2 Voltage <VC1, VC2 and VC3> for LCD driving
VC1, VC2 and VC3 are the voltages for LCD drive, and are generated by the LCD system regulated voltage
circuit and the LCD system voltage booster circuit to stabilize the display quality.
VC1 is generated by the LCD system regulated voltage circuit with VSS as the standard from the supply
voltage input from the VDD–VSS terminals.
VC2 and VC3 are respectively double and triple obtained from the LCD system voltage booster circuit.
The VC1 voltage can be adjusted to match the LCD panel characteristics by applying feedback to the VADJ
terminal using resistances RA1 and RA2 as shown in Figure 2.1.2.1.
The voltage VC1 (VSS standard) is shown by the following expression:
VC1
≈ 1 + RA2/RA1
Example:
VC1
Approx. 1 V
Approx. 1.5 V
RA1
∞
2 M
RA2
0
1 M
Fig. 2.1.2.1 VC1 adjustment circuit
See Chapter 7, "ELECTRICAL
CHARACTERISTICS" for the
voltage value.
2.2 Initial Reset
To initialize the S1C621C0 circuits, initial reset must be executed. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) Initial reset by the watchdog timer
Be sure to use reset function (1) when turning the power on and be sure to initialize securely. In normal
operation, the circuit may be initialized by any of the above two types.
Figure 2.2.1 shows the configuration of the initial reset circuit.
VC1
VADJ
RA2
(1 M
)
RA1
(2 M
)
VSS
-
+
VC1: 1.5V
VC1
VADJ
-
+
VC1: 1V
VSS
OSC1
OSC2
OSC1
oscillation
circuit
fOSC1
Dividing circuit
1 Hz
2 Hz
Watchdog
timer
R
S
Q
Internal
initial
reset
VDD
RESET
Fig. 2.2.1 Configuration of the initial reset circuit
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