參數(shù)資料
型號(hào)： S1C621C0D
元件分類(lèi)： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74
封裝： DIE-74
文件頁(yè)數(shù)： 59/108頁(yè)
文件大?。?/td> 992K
代理商： S1C621C0D
46
EPSON
S1C621C0 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller)
(2) Setting of carrier output width
In the soft-timer mode, the carrier output width (carrier output ON time) is controlled by writing to the
REMSO register, but in the hard-timer mode, it can be specified with values 0 to 15, which mean the
number of
τ cycles described above, in each transmission data bit. Since the carrier output ON/OFF is
controlled by the hardware in synchronizing with
τ waveform, it is unnecessary to watch the ON time
and to specify the OFF timing by the software.
The carrier output width can be selected by writing data to the ROUT3–ROUT0 register (E3H) from
among 16 types as shown in Table 4.9.5.3.
Table 4.9.5.3 Setting of carrier output width
ROUT3
0
1
ROUT2
0
1
0
1
Carrier output width
0
τ
1
τ
2
τ
3
τ
4
τ
5
τ
6
τ
7
τ
8
τ
9
τ
10
τ
11
τ
12
τ
13
τ
14
τ
15
τ
ROUT1
0
1
0
1
0
1
0
1
ROUT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
The carrier is output in synchronizing with the falling edge of the
τ waveform after writing data to
ROUT3–ROUT0 register. Data written to the ROUT3–ROUT0 register is maintained while the REM
circuit is ON until the next data is written. The carrier output starts using the write signal for this
register and the carrier output will be ON from the falling edge of the
τ waveform immediately after
that until the period set in the register has passed. In other words, the register data is valid only one
time after writing. Consequently, data must be written (possible with a logical arithmetic instruction)
every time even when outputting the same data successively.
The ROUT3–ROUT0 register is set to "0H" at initial reset and when both REMCR and REMDC registers
are set to "0". Consequently, after turning the REM circuit ON ("1" is written to the REMCR or REMDC
register), REMCR/REMDC output becomes low level (VSS) until a value other than "0H" is written to
the ROUT3–ROUT0 register.
Figure 4.9.5.2 shows the timing of data writing to the ROUT3–ROUT0 register and the carrier output.
Register writing
ROUT3–0
τ waveform
REMDC output
REMCR output
20
2
1
Fig. 4.9.5.2 Carrier output timing
Note: To prevent malfunction, do not write data to the ROUT3–ROUT0 register while
τ waveform is high.
Furthermore, the next transmission data writing should be done after the current carrier output is
completed unless done intentionally. If this register is written during carrier output, it stops output at
the point of the falling edge of the
τ waveform after the writing and starts new carrier output.
Those timings to be processed using interrupt are explained in the following section.
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