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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 18/108頁 |
| 文件大?。?/td> | 992K |
| 代理商： | S1C621C0D |
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S1C621C0 TECHNICAL MANUAL
EPSON
9
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER
4 PERIPHERAL CIRCUITS AND OPERATION
Peripheral circuits (timer, I/O, and so on) of the S1C621C0 are memory mapped, and interfaced with the
CPU. Thus, all the peripheral circuits can be controlled by using the memory operation command to access
the I/O memory in the memory map.
The following sections describe how the peripheral circuits operation.
4.1 Memory Map
Data memory of the S1C621C0 has an address space of 297 words, of which 48 words are allocated to
display memory and 41 words to I/O memory.
Figure 4.1.1 presents the overall memory maps of the S1C621C0, and Tables 4.1.1(a)–(c) the peripheral
circuits' (I/O space) memory maps.
In the S1C621C0 the same I/O memory has been laid out for each page 80H–FCH. As a result, the I/O
memory can be accessed without changing over the data memory page. The same result is obtained for I/O
memory changes and for readable/writable address references, no matter on what page it is done.
Note: The display memory area can be assigned to 050H–07FH or 450H–47FH by software.
When page 0 (050H–07FH) is selected: read/write is enabled.
When page 4 (450H–47FH) is selected: write only is enabled.
If page 0 is selected, RAM (48 words) is used as the display memory area.
Memory is not mounted in unused area within the memory map and in memory area not indicated
in this chapter. For this reason, normal operation cannot be assured for programs that have been
prepared with access to these areas.
Display memory 48 words
× 4 bits (W)
I/O memory
41 words
× 4 bits
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
HIGH
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
PAGE
LOW
ADDRESS
0
RAM 80 words
× 4 bits (R/W)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1
RAM 80 words
× 4 bits (R/W)
I/O memory
41 words
× 4 bits
I/O memory
41 words
× 4 bits
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
2
MF
ME
MD
MC
MB
MA
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
48 words
× 4 bits (R/W)
48 words
× 4 bits (R/W)
I/O memory
41 words
× 4 bits
Unused area
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
HIGH
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
PAGE
LOW
ADDRESS
3
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
4
I/O memory
41 words
× 4 bits
Display memory
or RAM
Fig. 4.1.1 Memory map
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