參數(shù)資料
型號： S1C621C0D
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74
封裝： DIE-74
文件頁數(shù)： 28/108頁
文件大小： 992K
代理商： S1C621C0D
18
EPSON
S1C621C0 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the input
ports K00–K03 and K10–K13, and can specify the terminal for generating interrupt and interrupt timing.
The interrupt selection register (SIK00–SIK03, SIK10–SIK13) select what input of K00–K03 and K10–K13 to
use for the interrupt. Writing "1" into an interrupt selection register incorporates that input port into the
interrupt generation conditions. The changing the input port where the interrupt selection register has been
set to "0" does not affect the generation of the interrupt.
The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that it
be generated at the falling edge according to the set value of the input comparison register (KCP00–
KCP03).
By setting these two conditions, the interrupt for K00–K03 and K10–K13 (4 bits unit) are generated when an
input port in which an interrupt has been enabled by the input selection register and the content of the
input comparison register have been changed from matching to no matching.
The interrupt mask registers EIK0 and EIK1 enable the interrupt mask to be selected for K00–K03 and K10–
K13, respectively.
When the interrupt is generated, the interrupt factor flag (IK0 for K00–K03, IK1 for K10–K13) is set to "1".
Figure 4.4.3.2 shows an example of an interrupt for K00–K03.
Interrupt selection register
Input comparison register
SIK03 SIK02 SIK01 SIK00
KCP03 KCP02 KCP01 KCP00
1
110
1010
With the above setting, the interrupt of K00–K03 is generated under the following condition:
Input port
(1)
K03
K02
K01
K00
1
0
1
0
(Initial value)
↓
(2)
K03
K02
K01
K00
1
011
↓
(3)
K03
K02
K01
K00
0
011
→ Interrupt generation
↓
(4)
K03
K02
K01
K00
0
111
Because K00 interrupt is set to disable, interrupt will be generated
when no matching occurs between the contents of the 3 bits K01–K03
and the 3 bits input comparison register KCP01–KCP03.
Fig. 4.4.3.2 Example of interrupt of K00–K03
4.4.3 Interrupt function
All 8 bits of the input ports (K00–K03, K10–K13) provide the interrupt function. The conditions for issuing
an interrupt can be set by the software. Further, whether to mask the interrupt function can be selected by
the software.
Figure 4.4.3.1 shows the configuration of K00–K03 (K10–K13) interrupt circuit.
Fig. 4.4.3.1 Input interrupt circuit configuration
Data
bus
Input comparison
register (KCP00, 10)
K00, 10
Interrupt
request
Interrupt selection
register (SIK00, 10)
Address
Interrupt factor
flag (IK0, 1)
K01, 11
K02, 12
K03, 13
Interrupt mask
register (EIK0, 1)
Address
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