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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 79/108頁 |
| 文件大?。?/td> | 992K |
| 代理商： | S1C621C0D |
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64
EPSON
S1C621C0 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.11 SVD (Supply Voltage Detection) Circuit
4.11.1 Configuration of SVD circuit
The S1C621C0 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the
source voltage lowers. Turning the SVD circuit ON/OFF can be controlled by the software.
The criteria voltage for evaluating the supply voltage is set to 2.3 V ± 0.15 V and whether the supply
voltage is more or less it can be read as data by the software.
Figure 4.11.1.1 shows the configuration of the SVD circuit.
VDD
Detection output
SVDDT
SVD circuit
VSS
Data
bus
SVDON
Fig. 4.11.1.1 Configuration of SVD circuit
4.11.2 SVD operation
When SVDON is set to "1", source voltage detection by the SVD circuit is executed. The SVD circuit com-
pares the criteria voltage (2.3 V ± 0.15 V) and the supply voltage (VDD–VSS). As soon as SVDON is reset to
"0", the result is loaded to in the SVDDT latch and SVD circuit goes OFF. By reading the data of this SVDDT
latch, it can be determined by means of software whether the supply voltage is normal or has dropped.
To obtain a stable SVD detection result, the SVD circuit must be on for at least l00 sec. So, to obtain the
SVD detection result, follow the programming sequence below.
Set SVDON to "1"
Maintain for 100 sec minimum
Set SVDON to "0"
Read SVDDT
However, when fOSC1 is selected for CPU system clock, the instruction cycles are long enough, so there is
no need to worry about maintaining 100 sec for SVDON = "1" in the software.
The detected data latched in SVDDT is maintained until the SVD circuit is operated again and a new
detection result is latched.
When SVD is on, the IC draws a large current, so keep SVD off unless it is.
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