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EPSON
S1C621C0 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller)
RCDTY: Carrier duty ratio selection (E1HD2)
Selects the duty ratio of the carrier.
Duty ratio set by RCDTY varies according to the carrier cycle set by RCDIV as the follows:
Table 4.9.6.2 Selection of carrier duty ratio
RCDIV
0
1
RCDTY
0
1
0
1
Carrier dividing ratio
fOSC3 / 8
fOSC3 / 12
fOSC3: OSC3 oscillation frequency
Carrier duty ratio
1/4
3/8
1/3
1/4
This setting must be done when the remote controller is OFF (REMCR = REMDC = "0") status.
At initial reset, this register is set to "0".
RT1, RT0:
τ cycle selection (E1HD1, D0)
Selects the
τ (reference cycle).
When controlling in the hard-timer mode, select the
τ (reference cycle) that is used as a reference for the
timing from the following table.
Table 4.9.6.3
τ (reference cycle) setting
RT1
0
1
RT0
0
1
0
1
τ dividing ratio
fcarrier / 12
fcarrier / 16
fcarrier / 20
fcarrier / 32
* fcarrier indicates carrier frequency. It
is selected by RCDIV (E1HD3).
This setting must be done when the remote controller is in OFF (REMCR = REMDC = "0") status.
At initial reset, these registers are set to "0".
ROUT3–ROUT0: Carrier output width selection (E3H)
When controlling in the hard-timer mode, select the carrier output width.
Table 4.9.6.4 Setting of carrier output width
ROUT3
0
:
1
ROUT2
0
:
1
Carrier output width
0
τ
1
τ
2
τ
:
14
τ
15
τ
ROUT1
0
1
:
1
ROUT0
0
1
0
:
0
1
By writing data to this register when the REMCR output has been enabled (REMCR = "1"), the carrier for
set
τ cycles is output from the REMCR (R00) terminal in synchronization with the falling edge of the τ
waveform immediately after that. If the REMDC output has been enabled, the REMDC output goes high
level (VDD) at the same timing, and is maintained for the set output width.
The setting (writing) of carrier output width must be done at every bit of the transmission data.
At initial reset and when both REMCR and REMDC registers are set to "0", this register is set to "0H
(0000B)".
Note: The ROUT3–ROUT0 register is for the exclusive use of the hard-timer mode. When controlling with
the soft-timer mode, be sure not to write data to this register to prevent malfunction.