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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 58/108頁 |
| 文件大小： | 992K |
| 代理商： | S1C621C0D |
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S1C621C0 TECHNICAL MANUAL
EPSON
45
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller)
The circuit in the hard-timer mode is configured as shown in Figure 4.9.1.2, and all the REM circuit is used.
However, the REMSO register that is used to control the carrier output in the soft-timer mode should be
fixed at "0". If "1" is written to the REMSO register, REMCR output and/or REMDC output are forcibly
done regardless of the control of the hard-timer mode.
(1)
τ (reference cycle)
τ (reference cycle) is used as reference for the carrier output ON time and interrupt timing specified by
the software, and is generated by the
τ (reference cycle) generation circuit by dividing carrier. This
dividing ratio can be selected using the RT1 and RT0 registers (E1HD1, D0) from 4 types as shown in
Table 4.9.5.1.
Table 4.9.5.1
τ (reference cycle) setting
RT1
0
1
RT0
0
1
0
1
τ dividing ratio
fcarrier / 12
fcarrier / 16
fcarrier / 20
fcarrier / 32
* fcarrier indicates carrier frequency. It
is selected with the RCDIV register
(E1HD3).
The actual time of
τ (reference cycle) can be found using the following expression according to the
OSC3 oscillation frequency, carrier cycle selection and the above selection.
τ (reference cycle) [sec] = 1 / (fOSC3 × DIV1 × DIV2)
fOSC3: OSC3 oscillation frequency
DIV1: Content of carrier dividing ratio set with the RCDIV register (1/8 or 1/12)
DIV2: Content of
τ dividing ratio set with the RT1 and RT0 registers (1/12, 1/16, 1/20 or 1/32)
Table 4.9.5.2 shows the examples of
τ (reference cycle) according to the OSC3 oscillation frequency.
Table 4.9.5.2
τ (reference cycle) examples
RCDIV
0
1
Register settings
RT1
0
1
0
1
455 kHz
0.211 msec (4739.6 Hz)
0.281 msec (3554.7 Hz)
0.352 msec (2843.8 Hz)
0.563 msec (1777.3 Hz)
0.316 msec (3159.7 Hz)
0.422 msec (2369.8 Hz)
0.527 msec (1895.8 Hz)
0.844 msec (1184.9 Hz)
RT0
0
1
0
1
0
1
0
1
OSC3 oscillation frequency
1 MHz
0.096 msec (10416.7 Hz)
0.128 msec (7812.5 Hz)
0.160 msec (6250.0 Hz)
0.256 msec (3906.2 Hz)
0.144 msec (6944.4 Hz)
0.192 msec (5208.3 Hz)
0.240 msec (4166.7 Hz)
0.384 msec (2604.2 Hz)
The carrier output ON time can be set to 16 types (0
τ to 15τ) based on the τ (reference cycle) set, so set
the
τ (reference cycle) after due consideration.
Figure 4.9.5.1 shows the
τ waveform when fcarrier /12 has been selected.
τ waveform is kept on outputting from the τ (reference cycle) generation circuit according to the set
dividing ratio while the REMCR register or REMDC register is "1".
Fig. 4.9.5.1
τ waveform (when fcarrier /12 is selected)
It is possible to set
τ (reference cycle) even if the OSC3 oscillation circuit is in OFF status. Furthermore,
when it is set once, the set contents are maintained until an initial reset is performed.
Note: The setting of the RT1 and RT0 registers should be done when the REM circuit is OFF (REMCR =
REMDC = "0") before starting remote transmission. Changing the contents when the REM circuit is
ON may cause a malfunction.
Carrier
τ waveform
τ
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