參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 95/111頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 84 of 111
APRIL 2006 – Revision 1.1
14.1.20
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h
Bit
Function
Type
Description
19:16
64-bit addressing
R/O
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
31:20
Prefetchable
Memory Limit
Address [31:20]
R/W
Defines the top address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be
FFFFFh.
14.1.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
Bit
Function
Type
Description
31:0
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
R/W
Defines the upper 32-bits of a 64-bit bottom address of an address
range for the bridge to determine when to forward memory read and
write transactions from one interface to the other.
Reset to 0
14.1.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
Bit
Function
Type
Description
31:0
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
R/W
Defines the upper 32-bits of a 64-bit top address of an address range
for the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
14.1.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
Bit
Function
Type
Description
15:0
I/O Base
Address, Upper
16-bits [31:16]
R/W
Defines the upper 16-bits of a 32-bit bottom address of an address
range for the bridge to determine when to forward I/O transactions
from one interface to the other.
Reset to 0
06-0057
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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