參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 36/111頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 30 of 111
APRIL 2006 – Revision 1.1
When the master repeats the transaction and starts transferring prefetchable read data from
data buffers while the read transaction on the target bus is still in progress and before a read
boundary is reached on the target bus, the read transaction starts operating in flow-through
mode. Because data is flowing through the data buffers from the target to the initiator, long
read bursts can then be sustained. In this case, the read transaction is allowed to continue
until the initiator terminates the transaction, or until an aligned 4KB address boundary is
reached, or until the buffer fills, whichever comes first. When the buffer empties,
PI7C8150A reflects the stalled condition to the initiator by disconnecting the initiator with
data. The initiator may retry the transaction later if data are needed. If the initiator does not
need any more data, the initiator will not continue the disconnected transaction. In this
case, PI7C8150A will start the master timeout timer. The remaining read data will be
discarded after the master timeout timer expires. To provide better latency, if there are any
other pending data for other transactions in the RDB (Read Data Buffer), the remaining
read data will be discarded even though the master timeout timer has not expired.
PI7C8150A implements a master timeout timer that starts counting when the delayed read
completion is at the head of the delayed transaction queue, and the read data is at the head
of the read data queue. The initial value of this timer is programmable through
configuration register. If the initiator does not repeat the read transaction and before the
master timeout timer expires (2
15 default), PI7C8150A discards the read transaction and
read data from its queues. PI7C8150A also conditionally asserts P_SERR_L (see Section
PI7C8150A has the capability to post multiple delayed read requests, up to a maximum of
four in each direction. If an initiator starts a read transaction that matches the address and
read command of a read transaction that is already queued, the current read command is not
posted as it is already contained in the delayed transaction queue.
See Section 5 for a discussion of how delayed read transactions are ordered when crossing
PI7C8150A.
3.6.7
FAST BACK-TO-BACK READ TRANSACTION
PI7C8150A can recognize fast back-to-back read transactions.
3.7
CONFIGURATION TRANSACTIONS
Configuration transactions are used to initialize a PCI system. Every PCI device has a
configuration space that is accessed by configuration commands. All registers are
accessible in configuration space only.
In addition to accepting configuration transactions for initialization of its own
configuration space, the PI7C8150A also forwards configuration transactions for device
initialization in hierarchical PCI systems, as well as for special cycle generation.
To support hierarchical PCI bus systems, two types of configuration transactions are
specified: Type 0 and Type 1.
06-0057
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