參數(shù)資料
| 型號： | PI7C8150ANDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 59/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
| 標準包裝： | 90 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-PBGA（17x17） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 51 of 111
APRIL 2006 – Revision 1.1
Table 5-1. These ordering rules apply to posted write transactions, delayed write and read
requests, and delayed write and read completion transactions crossing PI7C8150A in the
same direction. Note that delayed completion transactions cross PI7C8150A in the
direction opposite that of the corresponding delayed requests.
1. Posted write transactions must complete on the target bus in the order in which they
were received on the initiator bus. The subsequent posted write transaction can be setting a
flag that covers the data in the first posted write transaction; if the second transaction were
to complete before the first transaction, a device checking the flag could subsequently
consume stale data.
2. A delayed read request traveling in the same direction as a previously queued posted
write transaction must push the posted write data ahead of it. The posted write transaction
must complete on the target bus before the delayed read request can be attempted on the
target bus. The read transaction can be to the same location as the write data, so if the read
transaction were to pass the write transaction, it would return stale data.
3. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write data
traveling in the same direction. In this case, the read data is traveling in the same direction
as the write data, and the initiator of the read transaction is on the same side of PI7C8150A
as the target of the write transaction. The posted write transaction must complete to the
target before the read data is returned to the initiator. The read transaction can be a reading
to a status register of the initiator of the posted write data and therefore should not
complete until the write transaction is complete.
4. Delayed write requests cannot pass previously queued posted write data. For posted
memory write transactions, the delayed write transaction can set a flag that covers the data
in the posted write transaction. If the delayed write request were to complete before the
earlier posted write transaction, a device checking the flag could subsequently consume
stale data.
5. Posted write transactions must be given opportunities to pass delayed read and write
requests and completions. Otherwise, deadlocks may occur when some bridges which
support delayed transactions and other bridges which do not support delayed transactions
are being used in the same system. A fairness algorithm is used to arbitrate between the
posted write queue and the delayed transaction queue.
5.4
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data
delivery. The PCI Local Bus Specification, Revision 2.3, provides the following alternative
methods for synchronizing data and interrupts:
The device signaling the interrupt performs a read of the data just written (software).
The device driver performs a read operation to any register in the interrupting device
before accessing data written by the device (software).
System hardware guarantees that write buffers are flushed before interrupts are
forwarded.
06-0057
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C8150BNDIE | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| PI7C8152BMAIE | IC PCI-PCI BRIDGE 2PORT 160-MQFP |
| PI7C8154ANAE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C8154BNAIE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| PI7C9X110BNBE | IC PCIE TO PCI REV BRG 160LFBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
發(fā)布緊急采購，3分鐘左右您將得到回復。