參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁數(shù)： 54/111頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 47 of 111
APRIL 2006 – Revision 1.1
5
TRANSACTION ORDERING
To maintain data coherency and consistency, PI7C8150A complies with the ordering rules
set forth in the PCI Local Bus Specification, Revision 2.3, for transactions crossing the
bridge. This chapter describes the ordering rules that control transaction forwarding across
PI7C8150A.
5.1
TRANSACTIONS GOVERNED BY ORDERING RULES
Ordering relationships are established for the following classes of transactions crossing
PI7C8150A:
Posted write transactions, comprised of memory write and memory write and
invalidate transactions.
Posted write transactions complete at the source before they complete at the destination;
that is, data is written into intermediate data buffers before it reaches the target.
Delayed write request transactions, comprised of I/O write and configuration write
transactions.
Delayed write requests are terminated by target retry on the initiator bus and
are queued in the delayed transaction queue. A delayed write transaction must complete on
the target bus before it completes on the initiator bus.
Delayed write completion transactions, comprised of I/O write and configuration
write transactions.
Delayed write completion transactions complete on the target bus, and the target response
is queued in the buffers. A delayed write completion transaction proceeds in the direction
opposite that of the original delayed write request; that is, a delayed write completion
transaction proceeds from the target bus to the initiator bus.
Delayed read request transactions, comprised of all memory read, I/O read, and
configuration read transactions.
Delayed read requests are terminated by target retry on the initiator bus and are queued in
the delayed transaction queue.
Delayed read completion transactions, comprised of all memory read, I/O read, &
configuration read transactions.
Delayed read completion transactions complete on the target bus, and the read data is
queued in the read data buffers. A delayed read completion transaction proceeds in the
direction opposite that of the original delayed read request; that is, a delayed read
completion transaction proceeds from the target bus to the initiator bus.
PI7C8150A does not combine or merge write transactions:
PI7C8150A does not combine separate write transactions into a single write
transaction—this optimization is best implemented in the originating master.
06-0057
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PI7C8150B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge
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