參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 41/111頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 35 of 111
APRIL 2006 – Revision 1.1
Normal termination occurs when the initiator de-asserts FRAME_L at the beginning of the
last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction with
either TRDY_L or STOP_L assertion from the target.
Master abort
A master abort occurs when no target response is detected. When the initiator does not
detect a DEVSEL_L from the target within five clock cycles after asserting FRAME_L, the
initiator terminates the transaction with a master abort. If FRAME_L is still asserted, the
initiator de-asserts FRAME_L on the next cycle, and then de-asserts IRDY_L on the
following cycle. IRDY_L must be asserted in the same cycle in which FRAME_L de-
asserts. If FRAME_L is already de-asserted, IRDY_L can be de-asserted on the next clock
cycle following detection of the master abort condition.
The target can terminate transactions with one of the following types of termination:
Normal termination
TRDY_L and DEVSEL_L asserted in conjunction with FRAME_L de-asserted and
IRDY_L asserted.
Target retry
STOP_L and DEVSEL_L asserted with TRDY_L de-asserted during the first data phase.
No data transfers occur during the transaction. This transaction must be repeated.
Target disconnect with data transfer
STOP_L, DEVSEL_L and TRDY_L asserted. It signals that this is the last data transfer of
the transaction.
Target disconnect without data transfer
STOP_L and DEVSEL_L asserted with TRDY_L de-asserted after previous data transfers
have been made. Indicates that no more data transfers will be made during this transaction.
Target abort
STOP_L asserted with DEVSEL_L and TRDY_L de-asserted. Indicates that target will
never be able to complete this transaction. DEVSEL_L must be asserted for at least one
cycle during the transaction before the target abort is signaled.
3.8.1
MASTER TERMINATION INITIATED BY PI7C8150A
PI7C8150A, as an initiator, uses normal termination if DEVSEL_L is returned by target
within five clock cycles of PI7C8150A’s assertion of FRAME_L on the target bus. As an
initiator, PI7C8150A terminates a transaction when the following conditions are met:
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the
target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data
buffers to the target.
06-0057
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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