參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 66/111頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 58 of 111
APRIL 2006 – Revision 1.1
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR_L, the following events occur:
PI7C8150A sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
PI7C8150A asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C8150A has not detected the parity error on the secondary (initiator)
bus, which the parity error is not forwarded from the secondary bus to the
primary bus.
Assertion of P_SERR_L is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no
errors, there is no other way to signal this information back to the initiator. If the parity
error has forwarded from the initiating bus to the target bus, P_SERR_L will not be
asserted.
6.3
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C8150A to data parity errors are presented
according to the type of transaction in progress. This section organizes the responses of
PI7C8150A to data parity errors according to the status bits that PI7C8150A sets and the
signals that it asserts.
Table 6-1 shows setting the detected parity error bit in the status register, corresponding to
the primary interface. This bit is set when PI7C8150A detects a parity error on the primary
interface.
Table 6-1. Setting the Primary Interface Detected Parity Error Bit
Primary Detected
Parity Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / x
1
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
0
Delayed Write
Upstream
Primary
x / x
0
Delayed Write
Upstream
Secondary
x / x
06-0057
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