參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 64/111頁(yè)
文件大小： 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 56 of 111
APRIL 2006 – Revision 1.1
For downstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150A has write status to return, the following events occur:
PI7C8150A first asserts P_TRDY_L and then asserts P_PERR_L two cycles later, if
the primary interface parity-error-response bit is set in the command register.
PI7C8150A sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150A has write status to return, the following events occur:
PI7C8150A first asserts S_TRDY_L and then asserts S_PERR_L two cycles later, if
the secondary interface parity-error-response bit is set in the bridge control register
(offset 3Ch).
PI7C8150A sets the secondary interface parity-error-detected bit in the secondary
status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
PI7C8150A asserts P_PERR_L two cycles after the data transfer, if the following are
both true:
The parity-error-response bit is set in the command register of the primary
interface.
The parity-error-response bit is set in the bridge control register of the
secondary interface.
PI7C8150A completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the following
events occur:
PI7C8150A asserts S_PERR_L two cycles after the data transfer, if the following are
both true:
The parity error response bit is set in the command register of the primary
interface.
The parity error response bit is set in the bridge control register of the
secondary interface.
06-0057
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge
PI7C8150B-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge
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PI7C8150BMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMA-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
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