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參數(shù)資料
| 型號(hào)： | PI7C8150ANDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 83/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 73 of 111
APRIL 2006 – Revision 1.1
Support of the B2 secondary bus power state when in the D3 hot power management
state
Table 11-1 shows the states and related actions that PI7C8150A performs during power
management transitions. (No other transactions are permitted.)
Table 11-1. Power Management Transitions
Current Status
Next State
Action
D0
D3cold
Power has been removed from PI7C8150A. A power-up reset must
be performed to bring PI7C8150A to D0.
D0
D3hot
If enabled to do so by the BPCCE pin, PI7C8150A will disable the
secondary clocks and drive them LOW.
D0
D2
Unimplemented power state. PI7C8150A will ignore the write to the
power state bits (power state remains at D0).
D0
D1
Unimplemented power state. PI7C8150A will ignore the write to the
power state bits (power state remains at D0).
D3hot
D0
PI7C8150A enables secondary clock outputs and performs an internal
chip reset. Signal S_RST_L will not be asserted. All registers will
be returned to the reset values and buffers will be cleared.
D3hot
D3cold
Power has been removed from PI7C8150A. A power-up reset must
be performed to bring PI7C8150A to D0.
D3cold
D0
Power-up reset. PI7C8150A performs the standard power-up reset
functions as described in Section 12.
PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME#
signals do not pass through PCI-to-PCI bridges.
12
RESET
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
12.1
PRIMARY INTERFACE RESET
PI7C8150A has a reset input, P_RESET_L. When P_RESET_L is asserted, the following
events occur:
PI7C8150A immediately tri-states all primary and secondary PCI interface signals.
PI7C8150A performs a chip reset.
Registers that have default values are reset.
P_RESET_L asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLKOUT. PI7C8150A is not accessible during P_RESET_L. After P_RESET_L is de-
asserted, PI7C8150A remains inaccessible for 16 PCI clocks before the first configuration
transaction can be accepted.
06-0057
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
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