參數(shù)資料
型號(hào): PI7C8150ANDE
廠商: Pericom
文件頁數(shù): 47/111頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝: 90
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 40 of 111
APRIL 2006 – Revision 1.1
The delayed transaction queue is full, and the transaction cannot be queued.
A delayed read request with the same address and bus command has already been
queued.
A locked sequence is being propagated across PI7C8150A, and the read transaction is
not a locked transaction.
PI7C78150B is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
For posted write transactions:
The posted write data buffer does not have enough space for address and at least one
DWORD of write data.
A locked sequence is being propagated across PI7C8150A, and the write transaction is
not a locked transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator
must repeat the transaction with the same address and bus command as well as the data
if it is a write transaction, within the time frame specified by the master timeout value.
Otherwise, the transaction is discarded from the buffers.
3.8.4.2
TARGET DISCONNECT
PI7C8150A returns a target disconnect to an initiator when one of the following conditions
is met:
PI7C8150A hits an internal address boundary.
PI7C8150A cannot accept any more write data.
PI7C8150A has no more read data to deliver.
See Section 3.5.4 for a description of write address boundaries, and Section 3.6.3 for a
description of read address boundaries.
3.8.4.3
TARGET ABORT
PI7C8150A returns a target abort to an initiator when one of the following conditions is
met:
PI7C8150A is returning a target abort from the intended target.
06-0057
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