參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 61/111頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 53 of 111
APRIL 2006 – Revision 1.1
If the parity error response bit is set in the bridge control register, PI7C8150A does not
claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150A proceeds normally
and accepts transaction if it is directed to or across PI7C8150A.
PI7C8150A sets the detected parity error bit in the secondary status register.
PI7C8150A asserts P_SERR_L and sets signaled system error bit in status register, if
both of the following conditions are met:
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register.
6.2
DATA PARITY ERRORS
When forwarding transactions, PI7C8150A attempts to pass the data parity condition from
one interface to the other unchanged, whenever possible, to allow the master and target
devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C8150A.
6.2.1
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C8150A detects a data parity error during a Type 0 configuration write
transaction to PI7C8150A configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C8150A asserts
P_TRDY_L and writes the data to the configuration register. PI7C8150A also asserts
P_PERR_L. If the parity error response bit is not set, PI7C8150A does not assert
P_PERR_L.
PI7C8150A sets the detected parity error bit in the status register, regardless of the state of
the parity error response bit.
6.2.2
READ TRANSACTIONS
When PI7C8150A detects a parity error during a read transaction, the target drives data and
data parity, and the initiator checks parity and conditionally asserts PERR_L. For
downstream transactions, when PI7C8150A detects a read data parity error on the
secondary bus, the following events occur:
PI7C8150A asserts S_PERR_L two cycles following the data transfer, if the secondary
interface parity error response bit is set in the bridge control register.
06-0057
相關(guān)PDF資料
PDF描述
PI7C8150BNDIE IC PCI-PCI BRIDGE ASYNC 256-PBGA
PI7C8152BMAIE IC PCI-PCI BRIDGE 2PORT 160-MQFP
PI7C8154ANAE IC PCI-PCI BRIDGE ASYNC 304-PBGA
PI7C8154BNAIE IC PCI-PCI BRIDGE ASYNC 304-PBGA
PI7C9X110BNBE IC PCIE TO PCI REV BRG 160LFBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge
PI7C8150B-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge
PI7C8150BEVB 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8150BMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMA-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*