參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 16/111頁(yè)
文件大小： 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 12 of 111
APRIL 2006 – Revision 1.1
2
SIGNAL DEFINITIONS
2.1
Signal Types
Signal Type
Description
I
Input Only
O
Output Only
P
Power
TS
Tri-State bi-directional
STS
Sustained Tri-State. Active LOW signal must be pulled HIGH for 1 cycle when
deasserting.
OD
Open Drain
2.2
Signals
Note: Signal names that end with “_L” are active LOW.
2.2.1
PRIMARY BUS INTERFACE SIGNALS
Name
Pin #
Type
Description
P_AD[31:0]
49, 50, 55, 57, 58,
60, 61, 63, 67, 68,
70, 71, 73, 74, 76,
77, 93, 95, 96, 98,
99, 101, 107, 109,
112, 113, 115,
116, 118, 119,
121, 122
N3, T2, T4, N5,
P5, T5, N6, R5,
T6, P7, T7, R7,
T8, P8, R8, T9,
R12, P12, T14,
R13, N12, T15,
P16, N15, M14,
M13, M15,
L13, M16, L14,
L15, L16
TS
Primary Address / Data: Multiplexed address and data
bus. Address is indicated by P_FRAME_L assertion.
Write data is stable and valid when P_IRDY_L is
asserted and read data is stable and valid when
P_TRDY_L is asserted. Data is transferred on rising
clock edges when both P_IRDY_L and P_TRDY_L are
asserted. During bus idle, PI7C8150A drives P_AD to a
valid logic level when P_GNT_L is asserted.
P_CBE[3:0]
64, 79, 92, 110
R6, R9, T13,
N16
TS
Primary Command/Byte Enables: Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. After that, the initiator drives the byte enables
during data phases. During bus idle, PI7C8150A drives
P_CBE[3:0] to a valid logic level when P_GNT_L is
asserted.
P_PAR
90
N11
TS
Primary Parity. Parity is even across P_AD[31:0],
P_CBE[3:0], and P_PAR (i.e. an even number of 1’s).
P_PAR is an input and is valid and stable one cycle after
the address phase (indicated by assertion of
P_FRAME_L) for address parity. For write data phases,
P_PAR is an input and is valid one clock after
P_IRDY_L is asserted. For read data phase, P_PAR is
an output and is valid one clock after P_TRDY_L is
asserted. Signal P_PAR is tri-stated one cycle after the
P_AD lines are tri-stated. During bus idle, PI7C8150A
drives P_PAR to a valid logic level when P_GNT_L is
asserted.
06-0057
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