參數資料
型號： PI7C8150ANDE
廠商： Pericom
文件頁數： 20/111頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標準包裝： 90
系列： *
應用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應商設備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 16 of 111
APRIL 2006 – Revision 1.1
Name
Pin #
Type
Description
S_CLKOUT[9:0]
42, 41, 39, 38, 36,
35, 33, 32, 30, 29
M3, M2, N1,
L4, L3, M1, L2,
L1, K3, K2
O
Secondary Clock Output: Provides secondary clocks
phase synchronous with the P_CLK in synchronous
mode.
When these clocks are used, one of the clock outputs
must be fed back to S_CLKIN. Unused outputs may be
disabled by:
1. Writing the secondary clock disable bits in the
configuration space
2. Using the serial disable mask using the GPIO pins and
MSK_IN
3. Terminating them electrically.
2.2.4
MISCELLANEOUS SIGNALS
Name
Pin #
Type
Description
MSK_IN
126
K15
I
MSK_IN - Secondary Clock Disable Serial Input
(synchronous mode): This pin is used by PI7C8150A to
disable secondary clock outputs. The serial stream is
received by MSK_IN, starting when P_RESET is
detected deasserted and S_RESET_L is detected as
being asserted. The serial data is used for selectively
disabling secondary clock outputs and is shifted into the
secondary clock control configuration register. This pin
can be tied LOW to enable all secondary clock outputs
or tied HIGH to drive all the secondary clock outputs
HIGH.
P_VIO
124
K14
I
Primary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the primary bus. P_VIO
must be tied to 3.3V only when all devices on the
primary bus use 3.3V signaling. Otherwise, P_VIO is
tied to 5V.
S_VIO
135
G14
I
Secondary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the secondary bus.
S_VIO must be tied to 3.3V only when all devices on
the secondary bus use 3.3V signaling. Otherwise, S_VIO
is tied to 5V.
BPCCE
44
N2
I
Bus/Power Clock Control Management Pin: When
this pin is tied HIGH and the PI7C8150A is placed in
the D3HOT power state, it enables the PI7C8150A to
place the secondary bus in the B2 power state. The
secondary clocks are disabled and driven to 0. When this
pin is tied LOW, there is no effect on the secondary bus
clocks when the PI7C8150A enters the D3HOT power
state.
CFG66 /
SCAN_EN_H
125
K16
I
This is a multiplexed pin that has 2 functions.
CFG66 - 66MHz Configuration: This pin is used to
designate 66MHz operation. Tie HIGH to enable
66MHz operation or tie LOW to designate 33MHz
operation.
SCAN_EN_H - Full-Scan Enable Control
(synchronous mode): When SCAN_EN_H is LOW,
full-scan is in shift operation. When SCAN_EN_H is
HIGH, full-scan is in parallel operation. Note: Valid only
in test mode. Pin is CFG66 in normal operation.
06-0057
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參數描述
PI7C8150B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge
PI7C8150B-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge
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