參數(shù)資料
型號(hào)： PI7C8150ANDE
廠商： Pericom
文件頁(yè)數(shù)： 102/111頁(yè)
文件大小： 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類(lèi)型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 90 of 111
APRIL 2006 – Revision 1.1
14.1.35
UPSTREAM (S TO P) MEMORY LIMIT REGISTER – OFFSET 50h
Bit
Function
Type
Description
19:16
64 bit addressing
R/O
0: 32 bit addressing
1: 64 bit addressing
Reset to 1
31:20
Upstream
Memory Limit
Address
R/W
Controls upstream memory limit address.
Reset to 000FFFFFh
14.1.36
UPSTREAM (S TO P) MEMORY BASE UPPER 32-BITS REGISTER
– OFFSET 54h
Bit
Function
Type
Description
31:0
Upstream
Memory Base
Address
R/W
Defines bits [63:32] of the upstream memory base
Reset to 0
14.1.37
UPSTREAM (S TO P) MEMORY LIMIT UPPER 32-BITS
REGISTER – OFFSET 58h
Bit
Function
Type
Description
31:0
Upstream
Memory Limit
Address
R/W
Defines bits [63:32] of the upstream memory limit
Reset to 0
14.1.38
P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
1
Posted Write
Parity Error
R/W
Controls PI7C8150A’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
24 attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not assert if this event occurs.
Reset to 0
2
Posted Write
Non-Delivery
R/W
Controls PI7C8150A’s ability to assert P_SERR_L when it is unable
to transfer delayed write data after 2
24 attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
06-0057
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