參數(shù)資料
型號： PI7C8150ANDE
廠商： Pericom
文件頁數(shù)： 75/111頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 2PORT 256-PBGA
標(biāo)準(zhǔn)包裝： 90
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 66 of 111
APRIL 2006 – Revision 1.1
a locked posted write transaction, if the SERR_L enable bit is set in the command register.
Signal SERR_L is asserted for the master abort condition if the master abort mode bit is set
in the bridge control register (see Section 6.4).
8
PCI BUS ARBITRATION
PI7C8150A must arbitrate for use of the primary bus when forwarding upstream
transactions. Also, it must arbitrate for use of the secondary bus when forwarding
downstream transactions. The arbiter for the primary bus resides external to PI7C8150A,
typically on the motherboard. For the secondary PCI bus, PI7C8150A implements an
internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead.
This chapter describes primary and secondary bus arbitration.
8.1
PRIMARY PCI BUS ARBITRATION
PI7C8150A implements a request output pin, P_REQ_L, and a grant input pin, P_GNT_L,
for primary PCI bus arbitration. PI7C8150A asserts P_REQ_L when forwarding
transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least
one pending transaction resides in the queues in the upstream direction, either posted write
data or delayed transaction requests, PI7C8150A keeps P_REQ_L asserted. However, if a
target retry, target disconnect, or a target abort is received in response to a transaction
initiated by PI7C8150A on the primary PCI bus, PI7C8150A de-asserts P_REQ_L for two
PCI clock cycles.
For all cycles through the bridge, P_REQ_L is not asserted until the transaction request has
been completely queued. When P_GNT_L is asserted LOW by the primary bus arbiter
after PI7C8150A has asserted P_REQ_L, PI7C8150A initiates a transaction on the primary
bus during the next PCI clock cycle. When P_GNT_L is asserted to PI7C8150A when
P_REQ_L is not asserted, PI7C8150A parks P_AD, P_CBE, and P_PAR by driving them
to valid logic levels. When the primary bus is parked at PI7C8150A and PI7C8150A has a
transaction to initiate on the primary bus, PI7C8150A starts the transaction if P_GNT_L
was asserted during the previous cycle.
8.2
SECONDARY PCI BUS ARBITRATION
PI7C8150A implements an internal secondary PCI bus arbiter. This arbiter supports eight
external masters on the secondary bus in addition to PI7C8150A. The internal arbiter can
be disabled, and an external arbiter can be used instead for secondary bus arbitration.
8.2.1
SECONDARY BUS ARBITRATION USING THE INTERNAL
ARBITER
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN_L, must be tied
LOW. PI7C8150A has nine secondary bus request input pins, S_REQ_L[8:0], and has nine
secondary bus output grant pins, S_GNT_L[8:0], to support external secondary bus
masters.
06-0057
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