
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 32 of 111
APRIL 2006 – Revision 1.1
secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in
the downstream direction; that is, PI7C8150A generates a Type 0 transaction only on the
secondary bus, and never on the primary bus.
PI7C8150A responds to a Type 1 configuration transaction and translates it into a Type 0
transaction on the secondary bus when the following conditions are met during the address
phase:
The lowest two address bits on P_AD[1:0] are 01b.
The bus number in address field P_AD[23:16] is equal to the value in the secondary
bus number register in configuration space.
The bus command on P_CBE[3:0] is a configuration read or configuration write
transaction.
When PI7C8150A translates the Type 1 transaction to a Type 0 transaction on the
secondary interface, it performs the following translations to the address:
Sets the lowest two address bits on S_AD[1:0].
Decodes the device number and drives the bit pattern specified in
Table 3-6 on
S_AD[31:16] for the purpose of asserting the device’s IDSEL signal.
Sets S_AD[15:11] to 0.
Leaves unchanged the function number and register number fields.
PI7C8150A asserts a unique address line based on the device number. These address lines
may be used as secondary bus IDSEL signals. The mapping of the address lines depends on
the device number in the Type 1 address bits P_AD[15:11]. presents the mapping that
PI7C8150A uses.
Table 3-6. Device Number to IDSEL S_AD Pin Mapping
Device Number
P_AD[15:11]
Secondary IDSEL S_AD[31:16]
S_AD
0h
00000
0000 0000 0000 0001
16
1h
00001
0000 0000 0000 0010
17
2h
00010
0000 0000 0000 0100
18
3h
00011
0000 0000 0000 1000
19
4h
00100
0000 0000 0001 0000
20
5h
00101
0000 0000 0010 0000
21
6h
00110
0000 0000 0100 0000
22
7h
00111
0000 0000 1000 0000
23
8h
01000
0000 0001 0000 0000
24
9h
01001
0000 0010 0000 0000
25
Ah
01010
0000 0100 0000 0000
26
Bh
01011
0000 1000 0000 0000
27
Ch
01100
0001 0000 0000 0000
28
Dh
01101
0010 0000 0000 0000
29
Eh
01110
0100 0000 0000 0000
30
Fh
01111
1000 0000 0000 0000
31
10h – 1Eh
10000 – 11110
0000 0000 0000 0000
-
1Fh
11111
Generate special cycle (P_AD[7:2] > 00h)
0000 0000 0000 0000 (P_AD[7:2] = 00h)
-
06-0057