參數資料
| 型號： | PI7C8150ANDE |
| 廠商： | Pericom |
| 文件頁數： | 93/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
| 標準包裝： | 90 |
| 系列： | * |
| 應用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-PBGA（17x17） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 82 of 111
APRIL 2006 – Revision 1.1
Bit
Function
Type
Description
7:4
I/O Base Address
[15:12]
R/W
Defines the bottom address of the I/O address range for the bridge
to determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be 0. The upper 16 bits corresponding to address
bits [31:16] are defined in the I/O base address upper 16 bits address
register
Reset to 0
14.1.15
I/O LIMIT REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
11:8
32-bit Indicator
R/O
Read as 01h to indicate 32-bit I/O addressing
15:12
I/O Base Address
[15:12]
R/W
Defines the top address of the I/O address range for the bridge to
determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be FFFh. The upper 16 bits corresponding to
address bits [31:16] are defined in the I/O base address upper 16 bits
address register
Reset to 0
14.1.16
SECONDARY STATUS REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
20:16
Reserved
R/O
Reset to 0
21
66MHz Capable
R/O
Set to 1 to enable 66MHz operation on the secondary interface
Reset to 1
22
Reserved
R/O
Reset to 0
23
Fast Back-to-
Back Capable
R/O
Set to 1 to enable decoding of fast back-to-back transactions on the
secondary interface to different targets
Reset to 0
24
Master Data
Parity Error
Detected
R/WC
Set to 1 when S_PERR_L is asserted and bit 6 of command register
is set
Reset to 0
26:25
DEVSEL_L
timing
R/O
DEVSEL# timing (medium decoding)
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
27
Signaled Target
Abort
R/WC
Set to 1 (by a target device) whenever a target abort cycle occurs on
its secondary interface
Reset to 0
28
Received Target
Abort
R/WC
Set to 1 (by a master device) whenever transactions on its secondary
interface are terminated with target abort
Reset to 0
06-0057
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI7C8150B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
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