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參數(shù)資料
| 型號： | PI7C8150ANDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 67/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE 2PORT 256-PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
Page 59 of 111
APRIL 2006 – Revision 1.1
X = don’t care
Table 6-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C8150A detects a parity
error on the secondary interface.
Table 6-2. Setting Secondary Interface Detected Parity Error Bit
Secondary
Detected
Parity
Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
0
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
0
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
Table 6-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
PI7C8150A must be a master on the primary bus.
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
The P_PERR_L signal is detected asserted or a parity error is detected on the primary
bus.
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit
Primary
Data
Parity Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
1 / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
1 / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
1 / x
0
Delayed Write
Upstream
Secondary
x / x
X = don’t care
Table 6-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
06-0057
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| PI7C8154ANAE | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
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