參數(shù)資料
型號: PI7C8150ANDE
廠商: Pericom
文件頁數(shù): 3/111頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 2PORT 256-PBGA
標準包裝: 90
系列: *
應用: *
接口: *
電源電壓: *
封裝/外殼: 256-BGA
供應商設備封裝: 256-PBGA(17x17)
包裝: 管件
安裝類型: 表面貼裝
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
This mode of operation is valuable for design debugging and fault diagnosis since it
permits examination of connections not normally accessible to the test system. The
following subsections describe the boundary-scan test logic elements: TAP pins,
instruction register, test data registers and TAP controller. Figure 16-1 illustrates how
these pieces fit together to form the JTAG unit.
Figure 16-1
Test Access Port Block Diagram
16.1.1
TAP PINS
The PI7C8150A’s TAP pins form a serial port composed of four input connections (TMS,
TCK, TRST_L and TDI) and one output connection (TDO). These pins are described in
Table 16-1. The TAP pins provide access to the instruction register and the test data
registers.
16.1.2
INSTRUCTION REGISTER
The Instruction Register (IR) holds instruction codes. These codes are shifted in through
the Test Data Input (TDI) pin. The instruction codes are used to select the specific test
operation to be performed and the test data register to be accessed.
The instruction register is a parallel-loadable, master/slave-configured 5-bit wide, serial-
shift register with latched outputs. Data is shifted into and out of the IR serially through the
TDI pin clocked by the rising edge of TCK. The shifted-in instruction becomes active upon
latching from the master stage to the slave stage. At that time the IR outputs along with the
TAP finite state machine outputs are decoded to select and control the test data register
selected by that instruction. Upon latching, all actions caused by any previous instructions
terminate.
Page 100 of 111
APRIL 2006 – Revision 1.1
06-0057
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