參數(shù)資料
型號(hào): PI7C7300ANAE
廠商: Pericom
文件頁(yè)數(shù): 97/109頁(yè)
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告: Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝: 40
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 272-BBGA
供應(yīng)商設(shè)備封裝: 272-PBGA(27x27)
包裝: 管件
安裝類型: 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 88 OF 109
09/25/03 Revision 1.09
Bit
Function
Type
Description
11
Enable Primary
To Hold Request
Longer
R/W
Control’s PI7C7300A’s ability to hold requests longer at the Primary
Port.
0: internal Primary master will release REQ_L after FRAME_L
assertion
1: internal Primary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
15:12
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
14.1.38
MASTER TIMEOUT COUNTER REGISTER – OFFSET 74h
Bit
Function
Type
Description
31:16
Master Timeout
R/W
Holds the maximum number of PCI clocks that PI7C7300A will wait
for initiator to retry the same cycle before reporting timeout. Master
timeout occurs after 215 PCI clocks.
Default is 8000h.
14.1.39
RETRY COUNTER REGISTER – OFFSET 78h
Bit
Function
Type
Description
31:0
Retry Counter
R/W
Holds the maximum number of attempts that PI7C7300A will try
before reporting retry timeout. Retry count set at 224 PCI clocks.
Default is 0100 0000h.
14.1.40
SAMPLING TIMER REGISTER – OFFSET 7Ch
Bit
Function
Type
Description
31:0
Sampling Timer
R/W
Sets the duration (in PCI clocks) during which PI7C7300A will
record the number of successful transactions for performance
evaluation. The recording will start right after this register is
programmed and will be cleared after the timer expires. Maximum
period is 128 seconds at 33MHz.
Reset to 0.
14.1.41
SECONDARY SUCCESSFUL I/O READ COUNTER REGISTER –
OFFSET 80h
Bit
Function
Type
Description
31:0
Successful I/O
Read Counts on
S1 or S2
R/W
Stores the successful I/O read count on S1 or S2 and is updated when
the sampling timer is active.
Reset to 0
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