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參數(shù)資料
| 型號： | PI7C7300ANAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 58/109頁 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE 3PORT 272-BGA |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2010 |
| 標準包裝： | 40 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 272-BBGA |
| 供應(yīng)商設(shè)備封裝： | 272-PBGA（27x27） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 52 OF 109
09/25/03 Revision 1.09
!
PI7C7300A sets the data parity detected bit in the secondary status register, if the
secondary interface parity error response bit is set in the bridge control register.
!
PI7C7300A forwards the bad parity with the data back to the initiator on the primary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on
the primary bus, the data is discarded and the data with bad parity is not returned to
the initiator.
!
PI7C7300A completes the transaction normally.
For upstream transactions, when PI7C7300A detects a read data parity error on the
primary bus, the following events occur:
!
PI7C7300A asserts P_PERR# two cycles following the data transfer, if the primary
interface parity error response bit is set in the command register.
!
PI7C7300A sets the detected parity error bit in the primary status register.
!
PI7C7300A sets the data parity detected bit in the primary status register, if the
primary interface parity-error-response bit is set in the command register.
!
PI7C7300A forwards the bad parity with the data back to the initiator on the
secondary bus. If the data with the bad parity is pre-fetched and is not read by the
initiator on the secondary bus, the data is discarded and the data with bad parity is
not returned to the initiator.
!
PI7C7300A completes the transaction normally.
PI7C7300A returns to the initiator the data and parity that was received from the target.
When the initiator detects a parity error on this read data and is enabled to report it, the
initiator asserts PERR# two cycles after the data transfer occurs. It is assumed that the
initiator takes responsibility for handling a parity error condition; therefore, when
PI7C7300A detects PERR# asserted while returning read data to the initiator,
PI7C7300A does not take any further action and completes the transaction normally.
7.2.3
DELAYED WRITE TRANSACTIONS
When PI7C7300A detects a data parity error during a delayed write transaction, the
initiator drives data and data parity, and the target checks parity and conditionally asserts
PERR#.
For delayed write transactions, a parity error can occur at the following times:
!
During the original delayed write request transaction
!
When the initiator repeats the delayed write request transaction
!
When PI7C7300A completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address
parity, data, byte enable bits, and data parity are all captured and a target retry is returned
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7300ANA-E | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
| PI7C7300DNAE | 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C7300EVB | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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