
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 6 OF 109
09/25/03 Revision 1.09
4.10
CONCURRENT MODE OPERATION ....................................................................................... 40
5
ADDRESS DECODING .................................................................................................................... 40
5.1
ADDRESS RANGES ................................................................................................................... 40
5.2
I/O ADDRESS DECODING ........................................................................................................ 41
5.2.1
I/O BASE AND LIMIT ADDRESS REGISTER..................................................................... 42
5.2.2
ISA MODE............................................................................................................................ 42
5.3
MEMORY ADDRESS DECODING............................................................................................ 43
5.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ................................ 43
5.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ......................... 44
5.4
VGA SUPPORT ........................................................................................................................... 45
5.4.1
VGA MODE.......................................................................................................................... 45
5.4.2
VGA SNOOP MODE............................................................................................................ 46
6
TRANSACTION ORDERING.......................................................................................................... 46
6.1
TRANSACTIONS GOVERNED BY ORDERING RULES........................................................ 46
6.2
GENERAL ORDERING GUIDELINES...................................................................................... 47
6.3
ORDERING RULES .................................................................................................................... 48
6.4
DATA SYNCHRONIZATION .................................................................................................... 49
7
ERROR HANDLING......................................................................................................................... 50
7.1
ADDRESS PARITY ERRORS .................................................................................................... 50
7.2
DATA PARITY ERRORS ........................................................................................................... 51
7.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE ................. 51
7.2.2
READ TRANSACTIONS ....................................................................................................... 51
7.2.3
DELAYED WRITE TRANSACTIONS ................................................................................... 52
7.2.4
POSTED WRITE TRANSACTIONS...................................................................................... 55
7.3
DATA PARITY ERROR REPORTING SUMMARY ................................................................. 56
7.4
SYSTEM ERROR (SERR#) REPORTING.................................................................................. 60
8
EXCLUSIVE ACCESS...................................................................................................................... 61
8.1
CONCURRENT LOCKS ............................................................................................................. 61
8.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300A..................................................... 61
8.2.1
LOCKED TRANSACTIONS IN DOWSTREAM DIRECTION.............................................. 61
8.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION.................................................... 63
8.3
ENDING EXCLUSIVE ACCESS................................................................................................ 63
9
PCI BUS ARBITRATION................................................................................................................. 64
9.1
PRIMARY PCI BUS ARBITRATION......................................................................................... 64
9.2
SECONDARY PCI BUS ARBITRATION .................................................................................. 64
9.2.1
SECONDARY BUSARBITRATION USING THE INTERNAL ARBITER ............................. 64
9.2.2
PREEMPTION ..................................................................................................................... 66
9.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER.............................. 66
9.2.4
BUS PARKING.....................................................................................................................66
10
COMPACT PCI HOT SWAP ....................................................................................................... 67
11
CLOCKS ......................................................................................................................................... 67
11.1
PRIMARY CLOCK INPUTS....................................................................................................... 67
11.2
SECONDARY CLOCK OUTPUTS............................................................................................. 67
12
RESET............................................................................................................................................. 68
12.1
PRIMARY INTERFACE RESET ................................................................................................ 68
12.2
SECONDARY INTERFACE RESET .......................................................................................... 68