參數(shù)資料
型號： PI7C7300ANAE
廠商： Pericom
文件頁數(shù)： 85/109頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告： Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 77 OF 109
09/25/03 Revision 1.09
14.1.14
I/O BASE REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
3:0
32-bit Indicator
R/O
Read as 01h to indicate 32-bit I/O addressing
7:4
I/O Base Address
[15:12]
R/W
Defines the bottom address of the I/O address range for the bridge
to determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be 0. The upper 16 bits corresponding to address
bits [31:16] are defined in the I/O base address upper 16 bits address
register
Reset to 0
14.1.15
I/O LIMIT REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
11:8
32-bit Indicator
R/O
Read as 01h to indicate 32-bit I/O addressing
15:12
I/O Base Address
[15:12]
R/W
Defines the top address of the I/O address range for the bridge to
determine when to forward I/O transactions from one interface to
the other. The upper 4 bits correspond to address bits [15:12] and
are writable. The lower 12 bits corresponding to address bits [11:0]
are assumed to be FFFh. The upper 16 bits corresponding to
address bits [31:16] are defined in the I/O base address upper 16 bits
address register
Reset to 0
14.1.16
SECONDARY STATUS REGISTER – OFFSET 1Ch
Bit
Function
Type
Description
20:16
Reserved
R/O
Reset to 0
21
66MHz Capable
R/O
Set to 1 to enable 66MHz operation on the secondary (S1 or S2)
interface
Reset to 1
22
Reserved
R/O
Reset to 0
23
Fast Back-to-
Back Capable
R/O
Set to 1 to enable decoding of fast back-to-back transactions on the
secondary (S1 or S2) interface to different targets
Reset to 0
24
Data Parity Error
Detected
R/WC
Set to 1 when S1_PERR# or S2_PERR# is asserted and bit 6 of
command register is set
Reset to 0
26:25
DEVSEL#
timing
R/O
DEVSEL# timing (medium decoding)
00: fast DEVSEL# decoding
01: medium DEVSEL# decoding
10: slow DEVSEL# decoding
11: reserved
Reset to 01
27
Signaled Target
Abort
R/WC
Set to 1 (by a target device) whenever a target abort cycle occurs on
its secondary (S1 or S2) interface
Reset to 0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300DNAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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