參數(shù)資料
型號： PI7C7300ANAE
廠商： Pericom
文件頁數(shù)： 57/109頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告： Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 51 OF 109
09/25/03 Revision 1.09
!
If the parity error response bit is set in the bridge control register, PI7C7300A does
not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the
transaction to terminate in a master abort. If parity error response bit is not set,
PI7C7300A proceeds normally and accepts transaction if it is directed to or across
PI7C7300A.
!
PI7C7300A sets the detected parity error bit in the secondary status register.
!
PI7C7300A asserts P_SERR# and sets signaled system error bit in status register, if
both of the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the bridge control register.
7.2
DATA PARITY ERRORS
When forwarding transactions, PI7C7300A attempts to pass the data parity condition
from one interface to the other unchanged, whenever possible, to allow the master and
target devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C7300A.
7.2.1
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C7300A detects a data parity error during a Type 0 configuration write
transaction to PI7C7300A configuration space, the following events occur:
!
If the parity error response bit is set in the command register, PI7C7300A asserts
P_TRDY# and writes the data to the configuration register. PI7C7300A also asserts
P_PERR#. If the parity error response bit is not set, PI7C7300A does not assert
P_PERR#.
!
PI7C7300A sets the detected parity error bit in the status register, regardless of the
state of the parity error response bit.
7.2.2
READ TRANSACTIONS
When PI7C7300A detects a parity error during a read transaction, the target drives data
and data parity, and the initiator checks parity and conditionally asserts PERR#.
For downstream transactions, when PI7C7300A detects a read data parity error on the
secondary bus, the following events occur:
!
PI7C7300A asserts S_PERR# two cycles following the data transfer, if the
secondary interface parity error response bit is set in the bridge control register.
!
PI7C7300A sets the detected parity error bit in the secondary status register.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300DNAE 功能描述:外圍驅(qū)動器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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