參數(shù)資料
型號(hào)： PI7C7300ANAE
廠商： Pericom
文件頁數(shù)： 56/109頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告： Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝： 40
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 272-BBGA
供應(yīng)商設(shè)備封裝： 272-PBGA（27x27）
包裝： 管件
安裝類型： 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 50 OF 109
09/25/03 Revision 1.09
!
System hardware guarantees that write buffers are flushed before interrupts are
forwarded.
PI7C7300A does not have a hardware mechanism to guarantee data synchronization for
posted write transactions. Therefore, all posted write transactions must be followed by a
read operation, either from the device to the location just written (or some other location
along the same path), or from the device driver to one of the device registers.
7
ERROR HANDLING
PI7C7300A checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C7300A always tries to forward the existing
parity condition on one bus to the other bus, along with address and data. PI7C100
always attempts to be transparent when reporting errors, but this is not always possible,
given the presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C7300A implements the following:
!
PERR# and SERR# signals on both the primary and secondary interfaces
!
Primary status and secondary status registers
!
The device-specific P_SERR# event disable register
This chapter provides detailed information about how PI7C7300A handles errors. It also
describes error status reporting and error operation disabling.
7.1
ADDRESS PARITY ERRORS
PI7C7300A checks address parity for all transactions on both buses, for all address and
all bus commands. When PI7C7300A detects an address parity error on the primary
interface, the following events occur:
!
If the parity error response bit is set in the command register, PI7C7300A does not
claim the transaction with P_DEVSEL#; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C7300A proceeds
normally and accepts the transaction if it is directed to or across PI7C7300A.
!
PI7C7300A sets the detected parity error bit in the status register.
!
PI7C7300A asserts P_SERR# and sets signaled system error bit in the status register,
if both the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the command register.
When PI7C7300A detects an address parity error on the secondary interface, the
following events occur:
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7300ANA-E 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA
PI7C7300DNAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 3 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C7300EVB 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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