參數(shù)資料
型號: PI7C7300ANAE
廠商: Pericom
文件頁數(shù): 63/109頁
文件大小: 0K
描述: IC PCI-PCI BRIDGE 3PORT 272-BGA
產(chǎn)品變化通告: Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝: 40
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 272-BBGA
供應(yīng)商設(shè)備封裝: 272-PBGA(27x27)
包裝: 管件
安裝類型: 表面貼裝
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 57 OF 109
09/25/03 Revision 1.09
Primary Detected
Parity Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
0
Delayed Write
Upstream
Secondary
x / x
X = don’t care
Table 7-2 shows setting the detected parity error bit in the secondary status register,
corresponding to the secondary interface. This bit is set when PI7C7300A detects a
parity error on the secondary interface.
Table 7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT
Secondary
Detected Parity
Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
0
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
1
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
0
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
Table 7-3 shows setting data parity detected bit in the primary interface’s status register.
This bit is set under the following conditions:
!
PI7C7300A must be a master on the primary bus.
!
The parity error response bit in the command register, corresponding to the primary
interface, must be set.
!
The P_PERR# signal is detected asserted or a parity error is detected on the primary
bus.
Table 7-3 SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT
Primary Data
Parity Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
1 / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
1 / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
1 / x
0
Delayed Write
Upstream
Secondary
x / x
X = don’t care
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